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Programmable DC Electronic Load

HighTechPower

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Hi. I in normal routines have to design electronic switch mode power products. However to test them I want to built a programmable dc electronic load that can operate in CC, CV, CP, & CR modes plus other standard features. I have searched net for application notes but could not found any good material. I'm sharing this post in parallel so that if you know any good links for application notes or thesis.

Regards

Azeem
 

mtwieg

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If you only want standard features, why not just buy one off the shelf?
 
T

treez

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Well, you should search forums on this subject, because Eloads arent always that good for SMPS testing.
They have a feedback loop so can change the dynamics of your smps, which isnt very good if youre doing stability testing.
Also, they kind of act like they are adding capacitance to your smps.....so your smps's feedback loop gets changed, which again isnt good if you want to do eg transient response testing.
But if you just want to do thermal testing etc, then the eloads are quite good.
You just want a controllable fet and a big heatsink.
 

dick_freebird

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I would suggest making a plurality of loads
(CC, CV, CP, CR) individually, that will be a lot
simpler / easier / cleaner than a do-all box.
Simple (open loop) is good, I've seen E-loads
bother DC-DC stability as their control loop
adds to the mix in strange ways.

I like switched-resistor networks for a low-side
E-load - logic level FETs and drain resistors,
times however many bits of resolution you'd
like. That's your CR load ("constant enough"
if you use FETs that have Ron << Rexplicit). I
use this for CC testing if the output is DC(-ish).

Constant current, I like BJT current sources as
these can be made pretty simple and weighted.
Constant voltage is a bidirectional linear regulator
or, for high power, a DC-DC converter in current
mode if you can stand the noise.

Constant power is probably not happening
without a complex control loop. But I have never
had a call for contant-power testing, not one
that couldn't be gotten at by CC or CR and
human-in-the-loop adjusting for target level.
 

mtwieg

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Well, I'm hobbyist.
--- Updated ---

I want to make it myself.
Ok, fair enough.

A programmable CC load circuit is the heart of most electronic loads. The CC circuit can be made to imitate CV, CR, and CP behavior by applying a proper external feedback loop (generally done with a MCU). So start by making a solid CC circuit that meets your needs, then the rest becomes software.

Treez and Easy Peasy also mentioned potential issues with Eloads altering the transient response of your DUT. This definitely can happen, but generally isn't an issue unless you are specifically trying to characterize the DUT's control dynamics. In that case, you either need to ensure that the control of the Eload is much faster (and well damped) than the DUT. Or use open-loop methods like Easy Peasy mentioned.
 

volkwyr

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I have a lot of material on DC Electronic loads.
Best short white paper is the one from Keysight.
Best comprehensive whitepapers are a set of about 6 from Kikusui ( registration required to download).
There are numerous theses on internet - easily found with a Google search for (DC Electronic load thesis).

Basic load is CC. Programmable CR,CV and CP need analog multiplication (or an MDAC) for fast dynamic response. If fast response is not required, then a DSP or MCU can be used instead of an analog multiplier, as is commonly done in hobby projects, and also in several thesis projects.
Complete circuits that I have seen eg in online electronics magazines and also IC vendor application notes were mostly for CC mode only.

Above around 500W, if using MOSFETS, they should be paralleled. Standard power MOSFETS are designed for switching, not linear operation. Power MOSFETS have many cells in parallel on the silicon die, and these do not necessarily share current more or less equally in linear mode, which can lead to hot spots that can destroy a MOSFET . Very conservative design is required with switching MOSFETS ( ie operate well below rated power) and watch out that Safe Operating Area (SOA) is not exceeded. Linear MOSFETS cost much more, but do not have the risk of damage if operated within their power limits and SOA limits.
 

Easy peasy

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Do you understand de-rating of power curve for mosfets based on voltage and power and thermal interface material and heatsinking - and linear control loops given that the input capacitance to lots of mosfets in // is quite high ( slowing the performance )

We make electronic loads from 3kW ( 9V - 135V DC 0 - 120A ) and also some 200A & 300A up to 65VDC for telecom testing.

There is a lot more to the design than at first glance ....
 

schmitt trigger

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For a beginner, I would support the suggestion provided by several others above:
A resistive ladder switched with low side Mosfets would be both the easiest to design and most likely to be completed successfully.
 

HighTechPower

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Hi. As you can see in the attachments I have made ready schematics & PCB for my programmable DC electronic load. It consists of two PIC microcontrollers, four parallel power MOSFETS, graphical LCD interface, USB for data logging & RJ45 (to remote sense temperature digitally for batteries), intelligent fan cooling, heatsink temperature monitoring digitally, 5 SMD Chips along with other through hole ICs.
As my all design equipment is packed at the moment for long time so I'm waiting for the right time to bring it up when set office again.
 

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  • Azeem's High Tech Power 50.jpg
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Easy peasy

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what calcs have you performed for the power and dissipation in each mosfet ? Is there a fan on the heatsink ?
 

HighTechPower

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what calcs have you performed for the power and dissipation in each mosfet ? Is there a fan on the heatsink ?
I'm using MOSFETs IRLB4030PBF (Digikey part: IRLB4030PBF-ND) 100 V, 180 A, 4.3 m Ohm. I have a moderate size heatsink with fan on it and made PCB tracks of enough sizes to accommodate the maximum current demand by adding solder paste layer on top of both sides where applicable. Not shown here I will also scratch a big PCB rectangle solder masks just beneath heatsink base on both sides to add solder paste and then an insulator between top side and heatsink. It was by default on Altium PCB soft copy but may be you not see in actual board as I drew solder paste "polygon" for that and so did not appeared in PCB manufacturing (see attachment here for clarification). Just a wise guess, other than that no calculation performed to know power dissipation yet.
 

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  • Azeem's High Tech Power 49.jpg
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  • Azeem's High Tech Power 50.jpg
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KlausST

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Hi,

The resistance of solder paste compared to copper is so much higher that there is almost no benefit.
Better use thicker copper.

Klaus
 

Easy peasy

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you haven't said how many watts you would like to dissipate, best case would be for fan cooled and design for say 80 deg C on the 'sink

from the data sheet, the de-rating is 2.5W/degC ( above 25 deg C on the junc ) for the device and 0.4 degC / watt thermal R from junc to case, if we assume a heatsink with fan will give us 1 degC / watt rise, we need to allow for the thermal insulator between case and sink - even if only Si goo with AL2O3 ( the white thermal paste ) this will be another 0.5 degC/W at least. If the h-sink is sitting at 80degC and the ambient is 20 degC, then the max power you can dissipate is 60 watts, over 4 fets this is 15 watts per fet. If we really up the fan power we could perhaps get to 0.5 degC/watt, which would get us to 120 watts or 30W per fet.

We also need to refer to the DC SOA in the data sheet - but remember this is given for 175 degC junc and an infinite heatsink sitting at 25 degC keeping the case to 25degC.

Using our assumption in line 1 above, we have 80 degC on the heatsink ( fan cooled), and if we allow 150degC on the junc, the total thermal R is 0.9 degC/W, for a T delta of 150 - 80 = 70degC divided by 0.9degC/W = 77.7 watts of heat flow from the junc to the case

This is higher than the 30W per fet that the heatsink can actually get rid of - so we are heatsink limited to 30W / fet = 120watts

at this level the Tjunc will be 30 x 0.9 = 27 degC above 80 = 107 deg C

If you run these fets at slightly more power and raise the Tjunc ( and correspondingly the Tsink ) then you will run into issues of cell runaway inside the mosfets where the Vgs of a cell drops passing more current and heating further and dying. This is very prevalent when the Vds is above about 80V.

Don't be fooled by the 370W rating of the device - this is very largely fictional. ( 25degC baseplate, 175 degC junc )

Theoretically you could run each fet at 150degC junc at 30W each, this would mean the sink could be at 30 x 0.9 = 27 degC below this = 123degC on the 'sink - a hotter sink can shift more heat to the air by virtue of the delta T, even if we assume 0.4 degC / W ( for all four fets ) we arrive at 0.4 x 120W = 48 degC, subtracting this from 123degC = 75 degC ambient max, so you would have some headroom given that the Tamb might only climb to 35degC.

However the fets might not last too long at 150 Tjunc.

You might be interested to know that 30W is an industry maximum for dissipation for a TO-220 device - due to its small size, and hence small die size ....

p.s. for this device, the SOA curve only allows 10V @ 3ADC on an infinite h-sink giving 25degC case temp ....

Also just above the threshold voltage ( on the gate ) the gain of the device Gm = so many amps per volt of Vgs is very high - 320Siemens, i.e. 320A / volt of Vgs - this has real implications for the control loop ...!

Please do let us know what current and voltage you were intending to run the fets at ... ?
 
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HighTechPower

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Please do let us know what current and voltage you were intending to run the fets at ... ?
Not even decided yet however it must be above 60 Vmax and 50 Amax while keeping in safe operating area.
 

KlausST

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Hi,

this is 3000 Watts. That´s a lot of heat. You may heat a small house with that power.
Heatsink even with fan must be huge.

Klaus
 

Easy peasy

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Klaus is correct, unless that heatsink is water cooled, all you have really created is a fet wrecker, 750 watts per fet is not feasible, are you dissipating power else where ? i.e other than in four (?) fets ?
 

HighTechPower

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Not even decided yet however it must be above 60 Vmax and 50 Amax while keeping in safe operating area.
No not at all. I just means by saying this that upper limits must be 60 V or 50 A but not both at the same time. As an example 1 V x 50 A = 50 W, 30 V x 3 A = 90 W 60 V x 1 A = 60 W etc. I mentioned to keep in safe operating area but you took it wrong.
 

HighTechPower

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Hi. I'm closing business activities as Sole Proprietor (Design Engineer) High Tech Power. I'm shifting to mathematical physics in my leisure times in near future. As a gift please attached here find my schematics for programmable DC electronic load. It's also for evaluation purpose so that forum can benefit from it. Cheers!
 

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  • Electronic Load by Azeem's High Tech Power.PDF
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SunnySkyguy

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With a proper design spec any solution can be made with active loads.

- it requires a design for thermal resistance to not exceed a reliable junction temperature below 100'C and sufficient gain and phase margin in the loop bandwidth to control the DUT load with negative feedback. This may be compared with a reference to appear as a linear load with a GBW much greater than the DUT with low capacitance.

Layout and choice of components are important but ONLY come after a detailed design spec. (With the attributes like any component datasheet) Never start without a spec., which can be modified later to suit the requirements.

-If testing a MOSFET regulator then IGBT's would be suitable for high power and transistors for low power. Another metric is the T= RdsOn*Coss or Rce*Cce =T product was more than a decade lower than the DUY. Thus current sinks with Transistors and thermal feedback for balance current seems like a natural source... I mean sink..(lol)
The thermally bonded diode can act as a thermometer with suitable amplifiers to prevent the NTC effect on Vbe which can increase Ic if Vbe it was assumed to be constant without sensing input current.

- the cooling design must be no less critical than cooling a 100W CPU or a 300 Hp gasoline engine with attention to fluid linear surface velocity more than volume laminar flow. Air is also a fluid in thermal properties so linear surface velocities must be > 2m/s to achieve a much higher power transport coupling. For small heatsinks, this can be designed with turbulence rather than laminar flow over the hotspots then laminar flow for removal like an in-line fan to reduce blade noise yet draw high speed air over the fins.

- the thermal surface resistance depends greatly on co-planarity, roughness and (thermally and silver content) conductive grease to fill the nanopores only for an optimum result. Excess thickness increases the Rth and air voids are even worse.

- there are many standard solutions for adjustable current limiters that dissipate due to dropout excess heat, that can be minimized with a SMPS or phase control SCR AC bridge to pre-regulate for a low voltage drop. The latter was how Lambda did it in the 70's. The reference can be made with active current mirrors, with a bandgap Vref for controlling voltage and current or multiplying for power, dividing for resistance with linear or digital signal conditioners.
- For commercial use, a PFC is required for anything >100 W.

- load regulation is merely a step load and voltage response that indicates the DUT ESR after regulation due to linear gain limits for it's feedback. If the load regulation error was zero or negative, it could oscillate with sufficient gain. The lower the ESR of the load caps, the smaller the Pd gain in the DUT from sensing ripple and this causes lower phase margin and ringing error.

I will it it here before I write a book's worth of experience.

If you can imagine it, you can simulate it.
 
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