programmable Counter design help

[JoseNaveen]

i need to use a counter in my project ..the counter has a separate control register which can be written directly..based on the value written in the control register the freq of the counter is selected..can any1 help me with how this can be done..?

 

[vipinlal]

I think you need two processes in this design.

process(clk)

--divide this clock by some value so that the counter speed is properly set.

end process;


process(clk_divided)

--a typical counter program clocked at clk_divided.

end process;

the idea for the freq divider in the first process can be done understood from the following link:
A synthesizable delay generator instead of 'wait for' statement | VHDL coding tips and tricks
You may need to edit it in a proper way to use it in your design.

--vipin
VHDL coding tips and tricks