hi,
I think the most important is verification plan. and how to estimate functional coverage.
and as to tools, I think verilog is not very efficeint, I think maybe you can try systemverilog/systemc/vera/sugar/cycleC., etc.
they both are efficeint in simulation and have more power than hdl.
Basically, to verify a processor, u'd better build a functional model in C/C++. When simulating the RTL model with directed-random instructions, you may feed the same instructions to the C model and compare the execution result in Regfile/Mem in every several clock cycles.
1.build a C++/systemC verification enviroment.
2.generate some testbenchs for verifing your each block function.
3.do code coverage
4.generate systemic testbench to verifing your processor architecture.
5.do a direted random instructions series to test your design.
6.do a formal verificatiom