Hi, I am new to this forum, so if this post isn't in the right place let me know and I will move it! I am working on a hardware description language project that brings the modern software stack to hardware design. The idea is that it would be interoperable with SystemVerilog and provide a cleaner and more productive way of doing hardware design and verification. Here is a video that explains the main ideas. I am looking for feedback and collaborators, so let me know what you think!