kermit_the_frog
Newbie level 1
Hello,
I have a question that maybe someone can answer me:
Does anyone have experienced a bit inversion in a serial line, always in a fixed position of the message, due to a bad startup of the FPGA? We have a hardcode in the FPGA (the address of the unit, that is hardcoded in the FPGA pins) and we make two things with it:
1) Calculate a checksum of the serial message, that contains, between other things, the serialised hardcode: this is done correctly
2) Transmit a message containing several parameters, including the address: there is one bit inversion in a fixed position of the address, but the transmitted checksum is correct
The effect only happens for a certain harness length of the unit. We wondered of it was due to a bad startup combined to a high degree of sensitivity
Thanks in advance!
I have a question that maybe someone can answer me:
Does anyone have experienced a bit inversion in a serial line, always in a fixed position of the message, due to a bad startup of the FPGA? We have a hardcode in the FPGA (the address of the unit, that is hardcoded in the FPGA pins) and we make two things with it:
1) Calculate a checksum of the serial message, that contains, between other things, the serialised hardcode: this is done correctly
2) Transmit a message containing several parameters, including the address: there is one bit inversion in a fixed position of the address, but the transmitted checksum is correct
The effect only happens for a certain harness length of the unit. We wondered of it was due to a bad startup combined to a high degree of sensitivity
Thanks in advance!