Problems with pill packaging project (adder)

[WhiteLionGus]

Hi, this is my first time in the forum, so if I'm doing something wrong please let me know.

Well, my problem is that I'm building a circuit with vhdl with GAL 22v10d and everything was ok, until this part

Im sorry if the image is in spanish, but I'm from Mexico, by the way, I'm sorry for my bad english.
Anyway, I will try to explain you it in english.
Firstly, Im trying to do it with 4 bits so, (inside the red rectangle) there are (in order from left to right), a counter of 4 bits, then an adder, where the poblem begins, and a register. Well, the counter is going to count from 0 to 9, and then, the adder is going to receive the number coming (in binary code) from the counter, in other words, the register and the adder are going to be updating the sum. For those who program in c language it's like a for bucle. my problem is: how many bits must be the adder and the register?
For example, if I sum 9 with 9 I obtain 18, then, the counter works with 4 bits, and the adder obviously is going to receive 4 bits, so the adder works with four bits, but the number 18 in binary is represented like this: 10010, it hasn't 4 bits, so this is my problem, the adder has in one side 4 bits, and in the other side 7 bits because I wanna count until 99, the out is gonna work with 7 bits. How i do it? With logical gates? (in vhdl). Please help me.

 

[FvM]

I presume, if you know how to implement a 4 bit adder, you basically know how to make a 8 or 16 bit adder, so it's not quite clear to me what you are exactly asking.

The blcok diagram is showing a 8+16 bit adder, so it surely can't be implemented in a GAL22V10. I don't expect that you want to wire a large number of small logic devices to implement the design, although it's possible of course. But a single complex PLD would make your life much easier.

For the logic description, you have different levels of abstraction available, ranging from a hand coded gate level description to a behavioral VHDL design style.

 

[Analog Ground]

First, the 22V10 has only 10 registers in 10 macrocells. So, everything is not fitting in one device. The flip-flop count for your accumulator register is 7 (0-99). The number for the counter is 4 (0-9). Then, the adder needs some combinatorial logic. So, two 22V10 devices are necessary. One for the counter and one for the adder/accumulator. Perhaps someone can get WhiteLionGus started with the VHDL?

Correction - The adder and register cannot be fit in a single 22V10. The carry terms in each two bit, full adder propagate to the next full adder and will take up macrocells to feed back into the AND array. We are probably lookiing at four 22V10s. One for the counter, two for the adder and one for the register. Yes? No?