Problems in converting FPGA to ASIC

convert fpga to asic

I am learning how to use Design Compiler,so I try to synthesize one of my design which is implemented using Xilinx FPGA.Because I do not have a long-term project support,I can not get any help from the vendor and I encounter some problems listed below,Can anyone give some advices to help me ?So that I can synthesize my design using Design Compiler successfully

1.A multiplier is used in the datapath of my design and it is implemented using a Xilinx IP Core,can I use "*" directly in my RTL code for Design Compiler synthesis? Will it be synthsized just like the core gengerated by Design Ware??

2. A adder/substracter is also implemented using Xilinx IP core in my design,how can i write my RTL code to implement it for Design Complier Synthesis?

3.ROM,single port RAM,dual port RAM are all used in my design,how can I implement these without vendor's help?My goal is not optimization,functional implementation is acceptable.I mean that,at least, I can do the timing simulation using the sdf file generated by Design Complier.

Thanks a lot for your help!

u can do all our questions
u can specify adder in DC just tping what type adder u wanna include in ur design (CSA,RC ...)
u can change adder infer the adder .
i forgot the commands.
sorry

i will give you a script which flatten all DW components , you have to run script after compile and do a compile -incremental_mapping after script, it will solve all your doubt.
For security reasons i cant put script in foroum.

> 1. ... can I use "*" directly in my RTL code for Design Compiler synthesis?

Yes, the basic version of Design_Compiler will automatically turn the "*" operator into a DesignWare component. If you have more advanced DC license (like DC-Ultra, or Designware-Foundation), then the speed/area of the multiplier can be further improved.

> 2. A adder/substracter ...

Design Compiler has Designware components for all basic arithmetic operations (+, -, *, /, %.)

assign as_out = addsub ? ( a + b ) : ( a - b );

^^^Current versions of Design Compiler are smart enough to automatically convert this RTL into an addsub Designware unit.

> 3. ROM,single port RAM,dual port RAM are all used in my design,how can I implement these without vendor's help?

You can't...if the RAM/ROM is "small" (under 1000 total bits...), then you simply write the RAM/ROM using normal RTL-code. The synthesis-tool will use flipflops to implement your RAM/ROM -- this is not efficient, but usable.

The larger the memory-structure gets, the longer/harder Design Compiler will struggle to compile your memory. For example, if you are using the whole area of a BlockRAM (18Kbit), you will *NEED* the RAM-compiler toolset from your foundry vendor.

when you use rom ram or eeprom flash , you must consult your library vendor .

The adder/substractor is with carry out and carry in.If i write the RTL code just like the way i implement in C.Will it take too many gates? Suppose a and b are 32 bits,
when do substraction,i have to write one line of comparsion:
if(a>b)
..................

If i write the RTL code just like the way i implement in C.Will it take too many gates? Suppose a and b are 32 bits, when do substraction,i have to write one line of comparsion:
if(a>b)

Click to expand...

What do you mean by "too many gates"? For each arithmetic operation in your RTL-code, Design-Compiler will allocate/create 1 Designware instance to implement it. A compare-operation (<, >, <=, >=) will use slightly fewer gates than a conventional adder, because the compare-output is just a single-bit (true or false.)

The "basic" Design-Compiler license (DC-Basic or DC-Expert) are not smart enough to group/share arithmetic resources. For example:

assign sum1 = a + b;

assign sum2 = b + c;

assign sum3 = sum1 + c; // a + b + c

assign sum4 = a + sum2; // a + b + c

Click to expand...

The above causes Design Compiler to create a total of 4 adders. It's not "smart" enough to recognize the mathematical equivalent of sum3/sum4. The above math really only needs 2 adders (since sum3 and sum4 are equivalent.)

if ( (a + b) > (c + d) )
mysum = a+b;
else
mysym = c+d;
// DC synthesizes into 4 adders + 1 subtractor!

Click to expand...

^^^ This is another case where Design_Compiler will waste gates to build redundant adder/subtractor units.

// "Help" Design Compiler re-use resources
assign sum1 = a + b;
assign sum2 = c + d;

if ( sum1 > sum2 )
mysum = sum1;
else
mysum = sum2;

// ^^^ DC synthesizes into 2 adders + 1 subtractor.

Click to expand...

(Note, I think Design Compiler Ultra will auto-detect some of my examples, and automatically extract redundant operations.)