mhytr
Member level 3
convert fpga to asic
I am learning how to use Design Compiler,so I try to synthesize one of my design which is implemented using Xilinx FPGA.Because I do not have a long-term project support,I can not get any help from the vendor and I encounter some problems listed below,Can anyone give some advices to help me ?So that I can synthesize my design using Design Compiler successfully
1.A multiplier is used in the datapath of my design and it is implemented using a Xilinx IP Core,can I use "*" directly in my RTL code for Design Compiler synthesis? Will it be synthsized just like the core gengerated by Design Ware??
2. A adder/substracter is also implemented using Xilinx IP core in my design,how can i write my RTL code to implement it for Design Complier Synthesis?
3.ROM,single port RAM,dual port RAM are all used in my design,how can I implement these without vendor's help?My goal is not optimization,functional implementation is acceptable.I mean that,at least, I can do the timing simulation using the sdf file generated by Design Complier.
Thanks a lot for your help!
I am learning how to use Design Compiler,so I try to synthesize one of my design which is implemented using Xilinx FPGA.Because I do not have a long-term project support,I can not get any help from the vendor and I encounter some problems listed below,Can anyone give some advices to help me ?So that I can synthesize my design using Design Compiler successfully
1.A multiplier is used in the datapath of my design and it is implemented using a Xilinx IP Core,can I use "*" directly in my RTL code for Design Compiler synthesis? Will it be synthsized just like the core gengerated by Design Ware??
2. A adder/substracter is also implemented using Xilinx IP core in my design,how can i write my RTL code to implement it for Design Complier Synthesis?
3.ROM,single port RAM,dual port RAM are all used in my design,how can I implement these without vendor's help?My goal is not optimization,functional implementation is acceptable.I mean that,at least, I can do the timing simulation using the sdf file generated by Design Complier.
Thanks a lot for your help!