Hi Willebul,
Thanks a lot for your reply. I don't have the report here (the lab is close till Monday). But once I looked at the report and I think it told me that the longest delay is 55ns so since I was using 80MHz clock on board, I placed a component (essentially a counter) to slow down the clock to 10MHz, so I then used the slow clock to feed the main components of the design. I don't know if this is a wise way of handling it or not, or was there other ways to slow down the clock ...
At this point I do not have any major limitation on the timing, 10MHz is more than enough. I'll look at the timing analysis in more details and posted here as well (also please let me know if there was a better way of slowing down the clock)
Many thanks,
Mo.