Problems debugging Stratix FPGA

[mamadlin]

Hi All,

I have a design that has 4 identical components (essentially 4 ports swith of some sort) The FPGA device is Stratix S80. The design is not too big less than 2% of the device. I have set of FIFO's which are mapped to memory bits inside as well.

I have verified my design on Cadence NC-simulator. But when I put it on hardware it gives me weird results! 2 ports works and the others don't! At first I thought the problem is hardware (I have Rs232 transceivers but I swapped the pins, still the same ports were not working! I thought the pin assignment was not good=>no luck!) Then I looked at the code, if I change some unrelated code around other ports start working and one doesn't!!! I played around with compilation options (mainly removed couple of optimization just to test it!) and the behavior changed again (3 ports working one didn't!!)

I use Quartus II V4.2 for compilation and synthesis.

Any idea what could be the source of these weird problems? I'd appreciate any help and/or tips.

Many thanks,

Mo.

 

[Willebul]

Hi

What is your timing constraints and what does the timing analyst tell you after the compile.
Sounds like you are running into timing issues
Can you upload tour routing/timing report


Regards
W

 

[mamadlin]

Hi Willebul,

Thanks a lot for your reply. I don't have the report here (the lab is close till Monday). But once I looked at the report and I think it told me that the longest delay is 55ns so since I was using 80MHz clock on board, I placed a component (essentially a counter) to slow down the clock to 10MHz, so I then used the slow clock to feed the main components of the design. I don't know if this is a wise way of handling it or not, or was there other ways to slow down the clock ...

At this point I do not have any major limitation on the timing, 10MHz is more than enough. I'll look at the timing analysis in more details and posted here as well (also please let me know if there was a better way of slowing down the clock)

Many thanks,

Mo.

 

[mamadlin]

I checked the Timing Analysis report and there are lots of warnings stating that there is clock skew. Example:

Not operational: Clock Skew > Data Delay portprocessor:SOUTH_PORT|uart:UART_PORT|rs232_rx:rx_block|rx_state.stopping portprocessor:SOUTH_PORT|async_rx:ASYNC_RECV|async_state.idle clk clk None None 3.561 ns

In general, what can I do to solve the clock skew problems?

Appreciate any help/tips.

Thanks.

Mo.