Problem with Xilinx FPGA in a daisy chain mode

[dandynee]

fpga daisy chain problem

Hi, all,

I have a xilinx fpga board with 2 v2p-70 on in a daisy chain mode. and now I only need one fpga to work, in my case, it's the second fpga, and I found when I down load the bit file into it, it will not work but it will pass verify and if I download the second fpga after the first, it will work.

can anybody explain this to me? I guess there is something about the daisy chain that I don't know!

thanks in advance!

regards
D. Nee

 

[freeinthewind]

fpga daisy chain problem

I told u my experience . I often use Altera's FPGA. When I used multiple FPGAs, I connect all FPGA's "config_done" signal together .if all FPGAs are confurated successfully , they will relieve their "config_done" signals . Then the signal will be pulled up by external resistance. The signal become high level . if FPGAs detect the high level , they will initialize themself and enter user mode .then they can work effiently. i think Xilinx's FPGA work this way . that's my idea.

 

[wilbert_hj]

Re: fpga daisy chain problem

I told u my experience . I often use @ltera's FPGA. When I used multiple FPGAs, I connect all FPGA's "config_done" signal together .if all FPGAs are confurated successfully , they will relieve their "config_done" signals . Then the signal will be pulled up by external resistance. The signal become high level . if FPGAs detect the high level , they will initialize themself and enter user mode .then they can work effiently. i think Xilinx's FPGA work this way . that's my idea.

what is said above is right.
Actually,i designed a test board with 7 XC2VP70's in a daisy chain half a year ago,it works very well.when i download the bit file one by one manually, the FPGA's will work only if all the bit files have been downloaded.i have measured the IO pins before the completion,the IO voltage is not bound to any regular voltage standard.

 

[dandynee]

Re: fpga daisy chain problem

Thanks to all guys

so I got another question, why I must download the second after the first that the board will work and if I first download the second fpga and then down the first one, it will not work either?

thanks a lot!

BR

 

[dandynee]

Re: fpga daisy chain problem

when disconnect the done signal from the slave fpga, both the fpga can be programmed from jtag and boot right immediately, that is because the startup sequence of the fpga I think. When the fpga is programmed, it will release the done and then detect the done pin to check whether it is high or not, but the slave fpga is still not programmed, so it will pull the done low, this makes the master fpga to wait, that is the way when jtag mode, i think.

and when it comes to the prom mode, I really can not understand
when disconect the done of the slave fpga, the master will successfully booted from the first PROM (the done becomes high), and run immediately, but when connected, the done will never become high.

so what's wrong? does anybody know whether it is right to gen the mcs file seperately as the first prom for master fpga and the cascaded prom for slave fpga?