Re: fpga daisy chain problem
when disconnect the done signal from the slave fpga, both the fpga can be programmed from jtag and boot right immediately, that is because the startup sequence of the fpga I think. When the fpga is programmed, it will release the done and then detect the done pin to check whether it is high or not, but the slave fpga is still not programmed, so it will pull the done low, this makes the master fpga to wait, that is the way when jtag mode, i think.
and when it comes to the prom mode, I really can not understand
when disconect the done of the slave fpga, the master will successfully booted from the first PROM (the done becomes high), and run immediately, but when connected, the done will never become high.
so what's wrong? does anybody know whether it is right to gen the mcs file seperately as the first prom for master fpga and the cascaded prom for slave fpga?