chandra3789
Member level 1
Hi friends..
i have a big problem with the reference voltage which i have to supply to the pipelined ADC, i have designed, on chip.I have generated the two reference voltages 1.3 and 0.5 Volts(with a common mode voltage of 0.9 V) through low voltage band gap reference circuit. I have to supply these two voltages to the ADC through a unity gain buffer. All is well until here. When i supply the reference to the ADC, large currents are being drawn from the references by the ADC because of which the voltage is changing rapidly. The reason for this is the references may have to drive large capacitance at clock edges depending upon the digital outputs. The requirement for the circuit is the reference has to be very steady even though large currents (upto 6mA) are drawn from it otherwise the performance of the ADC will be severely affected. I have tried many possibilities like using regulators, decoupling capacitors etc. none of them solved the issue. I also have a plan of supplying the reference off chip but the bond wire inductance will exacerbate the problem. So, please suggest me what should i do?....waiting for replies.....
i have a big problem with the reference voltage which i have to supply to the pipelined ADC, i have designed, on chip.I have generated the two reference voltages 1.3 and 0.5 Volts(with a common mode voltage of 0.9 V) through low voltage band gap reference circuit. I have to supply these two voltages to the ADC through a unity gain buffer. All is well until here. When i supply the reference to the ADC, large currents are being drawn from the references by the ADC because of which the voltage is changing rapidly. The reason for this is the references may have to drive large capacitance at clock edges depending upon the digital outputs. The requirement for the circuit is the reference has to be very steady even though large currents (upto 6mA) are drawn from it otherwise the performance of the ADC will be severely affected. I have tried many possibilities like using regulators, decoupling capacitors etc. none of them solved the issue. I also have a plan of supplying the reference off chip but the bond wire inductance will exacerbate the problem. So, please suggest me what should i do?....waiting for replies.....