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Problem with the behaviour modeling ( spectre HDL) .........

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ramana.akula

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one ADC is designed, working nicely, But when the outputs of ADC is given to DAC(behaviour model not a design), then glitches are coming on the output's of ADC........ (i.e i/p's to DAC)

can anybody tell me the reason or resource for this pblm...

Thanks
Ram
 

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