problem with test*bench verilog at models*im

[Tom2]

i wrote the testbench bellow but unfortunately modelsim is not able to succesfull compile.i wonder if anyone can help me about this problem.


module tb_check();
reg in1,in2,Sel;
wire out;


check dut(out,in1,in2,sel); //
initial
begin
in1=1'b1;
in2=1'b0 ;
sel=1'b1 ;
#100;
in1=1'b0;
in2=1'b1 ;
sel=1'b0 ;
#100;
end
initial
begin
$monitor("in1=%b, in2=%b,sel=%b,out=%b, time=%t\n", in1,in2,sel,out, $time);
end
endmodule

 

[sv1437]

What is the error when you are compiling the testbench code?
If you are using Xilinx ISE, then there is no need to write the testbench code for testing your code. Just select the modelsim simulator and then you can change the inputs on the fly.

 

[Tom2]

I don't use Xilinx but only modelsim.The problem is that, can not generate the signal at the output.

 

[devas]

Hi,

When compiling your code with Modelsim I get 2 errors about signal sel. Remember Verilog is case sensitive! After changing this I do not get any compile error in the part you posted above.

Devas