Problem with synthesis of VHDL code

[dak-ju]

synthesis problem

Pls have a look at the following code in vhdl

if(clk'event and clk = 1) then
x <= y;
z <= x;
end if;

When I synthesize the code the rtl simulation shows z to be one clk cycle delayed version of y while in the netlist simulation it shows z to be two clk cycle delayed version of y(which should be the actual case.
My question are - is the above code perfect ? will it cause any problem in the validation of the h/w or will it be a problem in the final product on silicon?

Another observation that I would like to share is that if I add "after 1 ns " to line 2 and 3 of the above code I get perfect result in both rtl and netlist simulation.
Is it mandatory to add " after 1 ns" for all flop design?

Thanks and Regards
dak-ju

 

[nand_gates]

Re: synthesis problem

There is nothing wrong with the code! It must produce same result
both for RTL and Netlist simulation. This only means that there is some
problem with the simulator ur using! You have not mensioned which simulator,
which version and on which platfom you are using.

 

[silencer3]

synthesis problem

u must use "signal's" only for x,y,z. If u use variables, ur results will differ. this is due to delta delays. if use signals, u will get correct and same output in both rtl & gate-level simulations.

if this is not the case, then simulators also can have some impact based on options u use. pls check.

 

[dBUGGER]

synthesis problem

Hi dak-ju,
the post synthesis simulation must show the correctresults. You might be simulating pre-synthesis or behavioral model only. The post synthesis model must synthesize to a two flop structure y - x - z .

Best Regards,

 

[amaccormack]

Re: synthesis problem

Your code is correct for the circuit you want. Adding "after 1 ns" or "#1" in verilog is only done by those who dont understand the way that event based simulation works and is unnecessary. The fact that you use "<=" instead of ":=" shows that you have already correctly used signals, not variables.

 

[silverbyte]

Re: synthesis problem

I think your RTL simulation is not taking account of the blocking constructs. It is wrong.

 

[sp]

Re: synthesis problem

the problems i think is the process statement,,,, "if" is use in the process statement,,, signal inside a process is not instant... variable is the solution is u dont wanna hav this prob

When I synthesize the code the rtl simulation shows z to be one clk cycle delayed version of y while in the netlist simulation it shows z to be two clk cycle delayed version of y(which should be the actual case.

the 'z' get the previous value of 'x' and not after the 'y' is put into 'x'... please refer the

Circuit Design With VHDL, V. A. Pedroni; MIT Press

VHDL Programming by Example 4th Edition, Douglas L. Perry; McGraw Hill

for more on signal and varialbe in a process statement...

always remember signal assignment in a process is not instant...

my regards,
sp