Problem with segmentation when using VCS

[shweta_vlsi]

Hi all,
Im using VCS for my simulation, when I compile the design with VCS
It gives segmentation fault. Im using VCS2006 in RHEL3.
I use the commands
$vcs -debug file.v

 

[bigrice911]

Problem in using VCS

$vcs -debug -f file.v
if file.v is a verilog file list, you have to use '-f' to tell vcs you want to compile it instead to treat it as a verilog file.

 

[shweta_vlsi]

Re: Problem in using VCS

Hi bigrice911,
thansks for u reply, Im trying to compile only verilog file not the list of verilog files.

 

[aji_vlsi]

Re: Problem in using VCS

Hi all,
Im using VCS for my simulation, when I compile the design with VCS
It gives segmentation fault. Im using VCS2006 in RHEL3.
I use the commands
$vcs -debug file.v

Clear bug in tool, try their later/latest release. Else send test case to vcs_support <> synops...

Does it work without the -debug flag?

Ajeetha, CVC
www.noveldv.com