Problem with sampling of the outputs of a CARRY4 delay line chain

msdarvishi · Jul 20, 2015

Hello friends,

I would like to share my current issue with you and get your advise about it. I am working on a CARRY4 delay line based design in order to sample its output and in each clock rising edge, I would like to compare the sampled output with the old latched output by CARRY4 delay line chain.
I configured a delay line with CARRY4 primitives with 256 states that captures a digital signal called trigger coming from an LFSR (Linear Feedback Shift Register). At each rising clock transition of tdc_clock that is 400 MHz, I sample the captured signal by a DFlipFlop and compare it with its previous captured signal. As you see in the attached timing diagram, I provide the compared_output signal by subtracting the latched_output (captured by delay line) and thesampled_outout to detect any difference. A flag called ODC_result_sig will be raised if the comparison result is not 0. But I do not know why my compared result is not always 0 because I did not inject any extra delay to the digital signal and ODC_result_sig is raised unnecessarily. Could you please verify my timing diagram and give me your idea to figure out the problem?

I also send you my architecture for sampling and comparison as well as the definitions of sampling circuit and its initialization and the comparison method in the following:

------------------ Sampling circuit with DFF -----------------

Code VHDL - [expand]
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Inst_DFF: DFF PORT MAP(
D => latched_output_sig,
Q => sampled_output_sig,
QN => open,
CLK => clock_400MHz_AND,
RESET =>  sync_reset
);

-----------------------------------------------------------------

------------- writing a process for compared_output calculation -------

Code VHDL - [expand]
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process (clock_400MHz_AND, latched_output_sig, sampled_output_sig)
begin
  if(RISING_EDGE(clock_400MHz_AND)) then
   compared_output <= sampled_output_sig - latched_output_sig ;
   compared_output_1bit <= sampled_output_sig(255 downto 254) - latched_output_sig(255 downto 254);
   compared_output_first <= sampled_output_sig(15 downto 0) - latched_output_sig(15 downto 0);
  end if;
end process;

-----------------------------------------------------------------------

I thank in advance for your always kind consideration and assist.

ads-ee · Jul 20, 2015

I'm not at all sure how you expect any of this to work.

The delays from the AX to the DMUX carry output is 0.43 ns in the -3 speed grade of a Virtex 7. Given that you have 256 bits and 4-bits per CARRY4 means you have 64 CARRY4s, therefore 0.43*64 = 27.52 ns of cell delays alone. That isn't even close to being clockable at 400 MHz.

Besides that I'm not sure what your problem is with the simulation, so you delayed the latched_output with a register and called it sampled_output, since it's delayed unless the latched_output never changes the sampled_output will differ from the latched_output every time latched_output is updated with a new value. So the simulation waveform looks correct to me.

FvM · Jul 20, 2015

How is the trigger signal "captured" without a clock?

msdarvishi · Jul 20, 2015

FvM said:
How is the trigger signal "captured" without a clock?

The trigger signal is coming fro an LFSR circuit and it's like you see in the timing diagram...

- - - Updated - - -

ads-ee said:
I'm not at all sure how you expect any of this to work.

The delays from the AX to the DMUX carry output is 0.43 ns in the -3 speed grade of a Virtex 7. Given that you have 256 bits and 4-bits per CARRY4 means you have 64 CARRY4s, therefore 0.43*64 = 27.52 ns of cell delays alone. That isn't even close to being clockable at 400 MHz.

Besides that I'm not sure what your problem is with the simulation, so you delayed the latched_output with a register and called it sampled_output, since it's delayed unless the latched_output never changes the sampled_output will differ from the latched_output every time latched_output is updated with a new value. So the simulation waveform looks correct to me.

Thanks @ads-ee for your reply.
I do not car about those delays that you mentioned. I want to compare the latched_output signal with the sampled_output signal at each rising clock transition and detect any undesired delay occured in the trigger signal. I mean, if I inject a delay into the trigger signal, since its latched_output value is changed with the new clock cycle, it will be different as of sampled_output signal in the previous clock cycle. So, in this case, the compared_output must go to '1' state since the values of latched_output and sampled_output are different. But I see the compared_output signal varies between '0' and '1' states while no delay is injected into the latched_output signal !! It seems weird. I would cordially appreciate to have any suggestion by you.

Thanks,

ads-ee · Jul 20, 2015

msdarvishi said:
I do not car about those delays that you mentioned.

You should care it won't work in hardware. The primitive you are using is a carry chain, the AX-DMUX output delay defines the delay from end to end of the 256 bit chain. By the time you capture in sampled_output using the 400 MHz clock the chain has only propagated the carry around 5 CARRY4 primitives.

I still don't get why you think there is anything wrong with the simulation. compared_output changes on the clock edge every time sampled_output and latched_output are different. You can see it stops doing that when latched_output doesn't change for 4 clock cycles around 495 ns to 517 ns.

I'm thinking your problem with the waveform has more to do with not understanding 0 delay simulations and thinking the change in value should be captured at the leading clock edge instead of the trailing edge of the value change.

Code:

[FONT=Courier New]   __    __    __    __    __    __    __    __
__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |
__ _____ _____ _________________ _____ _____ ___
__X__a__X__b__X__c______________X__d__X__e__X___
__ _____ _____ _____ _________________ _____ ___
__X_____X__a__X__b__X__c______________X__d__X___
__ _____ _____ _____ _________________ _____ ___
__X_____X_a=?_X_b=a_X_c=b_X_c=c_______X_d=c_X___[/FONT]

Remember you are using this for compared_output:

Code VHDL - [expand]
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if(RISING_EDGE(clock_400MHz_AND)) then
   compared_output <= sampled_output_sig - latched_output_sig ;

Problem with sampling of the outputs of a CARRY4 delay line chain

msdarvishi

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Code VHDL - [expand]
1 2 3 4 5 6 7	Inst_DFF: DFF PORT MAP( D => latched_output_sig, Q => sampled_output_sig, QN => open, CLK => clock_400MHz_AND, RESET => sync_reset );

Code VHDL - [expand]
1 2	if(RISING_EDGE(clock_400MHz_AND)) then compared_output <= sampled_output_sig - latched_output_sig ;

Problem with sampling of the outputs of a CARRY4 delay line chain

msdarvishi

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