Problem with results of synthesizing with two frequencies

[they]

Synthesis problem

I have a design, which i try running synthesis with two frequency.
Is it possible that the area generated with the one with higher frequency is smaller than the one with lower frequency?

I am using Design Compiler.

 

[eda_wiz]

Synthesis problem

Higher frequency area will be usualy higher than low frequency area if everything else remains the same

 

[vikasjn]

Re: Synthesis problem

please recheck ur wire load model u may be using a very pessimistic ... or may have gone for overkill ... usally it is the other way around !!! I am assuming that all other constraints remain the same

 

[tutx]

Synthesis problem

Higher frequency - larger area, that is the truth if all other parametters are the same. Pls recheck/ reload your design.

 

[lionhunter]

Re: Synthesis problem

the area is still relative with dc optimization effort, and the PRI of area and timing is modifiable for dc optimization.

 

[tom123]

Re: Synthesis problem

high operating frequency usually need high speed and high drive logic,

these logic occupy more area than low speed logic, so it will need more area

to synthesize with operating frequency.

I have a design, which i try running synthesis with two frequency.
Is it possible that the area generated with the one with higher frequency is smaller than the one with lower frequency?

I am using Design Compiler.