Re: Help for a small problem
I did not wrote the testbench, i just forced all the parameters. When i tried with testbench i am getting some errors when i load the program. Please do not mind some mistakes i do, as iam a beginner.
force Address 0
force Data 1
force CS 0
force WE 0
run
force Address 1
force Data 0
run
force Data z
force WE z
force CS z
run
force CS 0
force OE 0
force WE 1
run
Here is the Test bench
module tbRamChip;
reg Address,Data,CS,WE,OE;
RamChip r1(Address,Data,CS,WE,OE);
initial
begin
Address=1'b0;Data=1'b1;CS=1'b0;WE=1'b0;OE=1'b1;
#20 Address=1'b1;Data=1'b0;CS=1'b0;WE=1'b0;OE=1'b1;
#30 Address=1'b0;CS=1'b0;WE=1'b1;OE=1'b0;
end
endmodule
This is the error i get when i try to load. it did not any thing when i compile.
# ERROR: C:/Documents and Settings/Administrator/Desktop/sri/RAMCHIP.V(5): Illegal output port connection (2nd connection).