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Problem with reading from Address to Data in a memory device

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Sathish

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Help for a small problem

Here is a small module. This is just a module of a memory device. I tried to force the values, i can write the value from 'Data' in to the 'Address' but i could not read from the 'Address' back to the 'Data'.

module RamChip (Address, Data, CS, WE, OE);
parameter AddressSize = 1;
parameter WordSize = 1;
input [AddressSize-1:0] Address;
inout [WordSize-1:0] Data;
input CS, WE, OE;
reg [WordSize-1:0] Mem [0:1<<AddressSize];
assign Data = (!CS && !OE) ? Mem[Address] : 1'bz;
always @(CS or WE)
if (!CS && !WE)
Mem[Address] = Data;
always @(WE or OE)
if (!WE && !OE)
$display("Operational error in RamChip: OE and WE both active");
endmodule

Plz suggest me. thankx...............
 

tarkyss

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Help for a small problem

change
assign Data = (!CS && !OE) ? Mem[Address] : 1'bz;
to
assign Data = (!CS && !OE && WE) ? Mem[Address] : 1'bz;
in addition, the width of (1'bz) must be equal with world size
always @(CS or WE) is not full
you'd better change to
always @(CS or WE or Address or Data)
 

Sathish

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Re: Help for a small problem

ya your idea is fine, but still it was not working, here i showed you the wave file in bmp format. i think now you can understand my problem.
 

tarkyss

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Help for a small problem

i just simulated it with modelsim
it is ok
can you show me your testbench?
 

Sathish

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Re: Help for a small problem

I did not wrote the testbench, i just forced all the parameters. When i tried with testbench i am getting some errors when i load the program. Please do not mind some mistakes i do, as iam a beginner.

force Address 0
force Data 1
force CS 0
force WE 0
run
force Address 1
force Data 0
run
force Data z
force WE z
force CS z
run
force CS 0
force OE 0
force WE 1
run

Here is the Test bench
module tbRamChip;
reg Address,Data,CS,WE,OE;
RamChip r1(Address,Data,CS,WE,OE);
initial
begin
Address=1'b0;Data=1'b1;CS=1'b0;WE=1'b0;OE=1'b1;
#20 Address=1'b1;Data=1'b0;CS=1'b0;WE=1'b0;OE=1'b1;
#30 Address=1'b0;CS=1'b0;WE=1'b1;OE=1'b0;
end
endmodule
This is the error i get when i try to load. it did not any thing when i compile.
# ERROR: C:/Documents and Settings/Administrator/Desktop/sri/RAMCHIP.V(5): Illegal output port connection (2nd connection).
 

tarkyss

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Re: Help for a small problem

i think you testbench is error
at first, data is a inout port
so it must be wire type
but if you want to asign it in initial command
it must be reg type
so you can define a reg type val(for example datar)
and then
assign datar=(!CS && !OE && !WE)? datar : 1'bz
 

Sathish

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Re: Help for a small problem

thanx tar, it worked out
 

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