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Problem with post layout simulation

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lizeer

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post_layout simulation

hi,
I am doing post layout simulation and have a signal which it path through several combinational logic and lastly is a DFF.
when the signal arrived at DFF at the value is changed from 1 to 0 about 1ns from the next clock cycle, value of Q for the next clock cycle is unchanged (still '1').
I already done the STA for this path but there are no violation for setup and hold time.
Please give comment about this situation.
 

Nandy

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post_layout simulation

You need $sdf_annotate task in your testbench to back annotate SDF from postlayout. Or setup check time will be default unit time 1ns.

Nandy
www.nandigits.com
Nelist Debug/ECO in GUI mode
 

jjww110

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post_layout simulation

use -sdf max
 

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