lizeer
Newbie level 5
post_layout simulation
hi,
I am doing post layout simulation and have a signal which it path through several combinational logic and lastly is a DFF.
when the signal arrived at DFF at the value is changed from 1 to 0 about 1ns from the next clock cycle, value of Q for the next clock cycle is unchanged (still '1').
I already done the STA for this path but there are no violation for setup and hold time.
Please give comment about this situation.
hi,
I am doing post layout simulation and have a signal which it path through several combinational logic and lastly is a DFF.
when the signal arrived at DFF at the value is changed from 1 to 0 about 1ns from the next clock cycle, value of Q for the next clock cycle is unchanged (still '1').
I already done the STA for this path but there are no violation for setup and hold time.
Please give comment about this situation.
