entity testip is
port (
...
fifo_dataout : in std_logic_vector(0 to 31);
ip_dataout : in std_logic_vector(0 to 31);
ip_ce : out std_logic;
ip_we : out std_logic;
ip_datain : out std_logic_vector(0 to 31);
);
end entity testip;
architecture imp of testip is
signal ip_ce_ns : std_logic;
signal ip_we_ns : std_logic;
signal ip_ce_cs : std_logic;
signal ip_we_cs : std_logic;
signal ip_dataout_i : std_logic_vector(0 to 31);
...
begin
COMB : process (...)
begin
ip_ce_ns <= ip_ce_cs;
ip_we_ns <= ip_we_cs;
case ip_nstate_cs is
when IDLE =>
...
end case;
end process COMB;
REG: process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ip_ce_cs <= '1';
ip_we_cs <= '1';
...
else
ip_ce_cs <= ip_ce_ns;
ip_we_cs <= ip_we_ns;
...
end if;
end if;
end process REG;
S0: ip_ce <= ip_ce_cs;
S1: ip_we <= ip_we_cs;
S2: ip_datain <= fifo_dataout;
S3: ip_dataout_i <= Ip_dataout;
end architecture imp;