Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The Q and Q' curves suggests Q stays high longer than the midway, switching voltage Vm is higher than Vdd/2. This can be caused by the fact that in the ouptut inverter stages, PMOS is stronger than the NMOS.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
