How the simulator decide the Q and QBar of the SR latch terminal

[Awalluddin]

Hi everyone, an SR latch that build using Nand gate, how do the simulator decide the Q and QBar terminal. The SR latch is symmetry, and either the terminal could be Q and vice versa.

 

[D.A.(Tony)Stewart]

If both inputs were low , the last one to go high asserts both output states to be complementary.
Otherwise if the inputs are exclusive, it is obvious. Using de Morgan’s it could also be +ve input logic using NOR gates and swapping output labels

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… Negative input logic which ought to be labelled like Q-bar

 

[dick_freebird]

The simulator doesn't assign topology. You do. In the
netlist and in your mind (the two should agree).

 

[crutschow]

If you are referring as to how the simulator comes up at the start, it's purely arbitrary if S and R are both high, unless you assign a state (and you should).

 

[D.A.(Tony)Stewart]

The simulator applies simple rules of logic of a NAND gate with analog voltages and assumed thresholds for the logic family and Vdd.

S R Q Q
1 1 x x ( no change, x previous state but complementary)
0 1 1 0
1 1 1 0 ( previous state latched)
1 0 0 1
1 1 0 1 ( previous state latched)
0 0 1 1 ( illegal states as SR state will become valid (complimentary outputs ) when 1st SR goes high)

--- Updated Nov 12, 2023 ---