problem with LDO design!

[imar]

thanks LvW for these new information, i was thinking that phase margen is usually calculated referring to -180°!
so, i tryed to adjust the compensation scheme for high load current (100mA) and by varying the pass element transistor to work in the saturation region, i found that the output voltage is 2.8V which is the desired value ( by a trans simulation), i run then the Ac simulation. you can find the results joined.

 

[imar]

the ac simulation for load current variation

 

[LvW]

thanks LvW for these new information, i was thinking that phase margen is usually calculated referring to -180°!

Yes, I know - sometimes it is confusing.
The reason is as follows: Some books and some people (mostly for control system design) define the loop gain WITHOUT the minus sign which is introduced by comparing the output with the required value in the error amp (case 1). Some other sources take this inverting operation into consideration by defining the loop gain (case 2), what I think is the most logical way.
In case 1 the margin is defined against -180 deg (identical to a critical point in the Nyquist plot at -1). In case 2 the margin is defined against zero deg. and the critical Nyquist point is at +1.
Both cases can be found in the literature and it is important to know the background.

To your plots: They look nice, and I think the margins for all three alternatives are sufficient. So - problems solved ?

 

[ashish_chauhan]

It appears from your load step response ... that you are trying to model the load using a pulsating current source and not by resistor(which is correct way)

also , as per ur specs(what u had posted) the dropout can not be more than 170mV
but ur sims probably are showing much moe than that...?

 

[imar]

thank you LvW and ashish_chauhan for your help

for LvW: the circuit is now stable but i have to improve only the trans simulation to make the Vout more stable without fluctuations ( around 2.8V) .

for ashish_chauhan : the spec that i posted aren't my specs that i am working on. but only i tried to understand the point that the output voltage could be variable. SO it is another spec. In my work, i have to maintain Vout to 2.8V inder a dropout voltage of 0.5V.the trans simulation, that i posted, prouve that there is more work concerning enhancement of it by reducing the fluctuation (from 2.8 to 2.2V).

Added after 5 hours 13 minutes:

i am trying now to use the ESR method

and these are the simulation responses. i think that they appear good; isn't it?

 

[imar]

[No message]

 

[LvW]

It appears from your load step response ... that you are trying to model the load using a pulsating current source and not by resistor(which is correct way.

Hi imar, ashhish_chauhan is right - finally you should use resistors instead of current sources to model different load conditions. The behaviour is different in the time domain !

 

[imar]

that is what happen but hopefully the variation is not harmful!
because for low resistance around 35 Ω the output voltage is 2.796V and for higher value (from 100Ω to 2.5KΩ), the Vout still around 2.801V.

 

[LvW]

that is what happen but hopefully the variation is not harmful!
because for low resistance around 35 Ω the output voltage is 2.796V and for higher value (from 100Ω to 2.5KΩ), the Vout still around 2.801V.

Well, I think this looks very good. Congratulations.

 

[imar]

i tried also to know the impact of varying the input voltage Vin from 3.3V to 3V with a trans simulation and i ploted the Vout as follows.

can i extract from this simulation the PSRR of the circuit?

 

[ashish_chauhan]

well on an approximate level yes...

ur simulation results show a dip of around 6mv for a change of 300mv in the vin ..

so u can take the psr to be roughly as 34dB...

for exact figures its better to go for ac simulations with ac signal added on to ur supply and give a freq sweep(simulator itself does that) and measure the ratio of
Δvout/Δvin in decibels...

note that ur psrr sim values will be different for different loads... it will reduce for higher loads.

another note of caution: in the last ac sim result u have attached... i see that u have huge dip in phase which makes phase margin as low as 28deg... this may degrade even further across process and will cause excessive ringing in the output or may even may cause oscillations... so try to mAKE IT atleast 35+ across corner...

 

[LvW]

....................
another note of caution: in the last ac sim result u have attached... i see that u have huge dip in phase which makes phase margin as low as 28deg...

How do you derive this value ??? Did I miss any diagram ?

 

[ashish_chauhan]

probably yes ...

in the last attached ac sim result there is a dip in phase curve which is minimum at 7kHz. and the value is well below 30 deg line... and that is the phase margin..

 

[LvW]

probably yes ...
in the last attached ac sim result there is a dip in phase curve which is minimum at 7kHz. and the value is well below 30 deg line... and that is the phase margin..

Thank you, ashish_chauhan, for posting the diagram a second time.
However, it does NOT look critical, since the phase margin is defined at the frequency for which the gain crosses the 0 dB line.
This effect is a typical result of a frequency compensation network: to enhance the phase in a region where the loop gain is app. 0 dB.
Thus, the PM is as indicated in the diagram - that means it is large enough.

Hello imar: It looks good !

 

[ashish_chauhan]

well its right that pm is defined at freq where gain is 0dB. but u need to ensure enough margin through the loop bandwidth because as the corner changes some of the parasitic poles may get in the bandwidth range and degrade ur good margin.

we never encourage this kind of phase response... it is always risky!!

imar, I wont recommend this specially when its a typical response.

 

[imar]

thanks for you two!

it is a very useful conversation that you have done yesterday and it worried me at the moment that the phase margin has to be rearranged.
what makes me feel not so troubled is when LvW tryied to reconsole me! Thanks again LvW
so i will try to enhance the PM at the deep point to reach if it is possible to 35° as Ashish said. Thanks Ashish.
i will verify the PSRR for other load value.
i am now trying to go deeper in the simulation to find if there are other issues that should be verified like line regulation, quescient current, efficiency ...
i will post the results!
thanks again.

 

[ashish_chauhan]

ur transient response for changing vdd was itself a reading of line regulation...

simply divide the change in o/p value by change in vdd... and thats the reading.

 

[imar]

thanks
so the PSRR and line regulation could be expressed by the same expression, except that PSRR is a
small signal parameter at a particular frequency.

also the load regulation could be measured by changing the load current and measuring the changes in output voltage. so it could derivated from the trans response for a load current variation.

isn't it?

 

[ashish_chauhan]

yes it is , but you need to vary the load using a resistance and not a current source... as I pointed out in one of my previous posts.

you can probably model ur load with a mos and then easily switch it on and off for better evaluation...

 

[imar]

ok i have replaced it already

thanks

Added after 1 hours 48 minutes:

i achieved the load current simulation and i found that the output variation is about 82mV for a load current that vary frrom 1mA to 100mA.

i also verified the stability with AC simulation and the deep point of the phase has been emprouved for only few degrees, also the minimum phase margin is 47°.

the only point that i don't really know how to manage is the calculation of the quiescent current by Cadence; theoretically, Quiescent, or ground current, is the difference between input and output currents.

could the input current be the one that is feeding the error ampli and the bandgap or what?
how can i simulate this quiscent current?

thanks for help