imar said:i am trying first to enhance the error amplifier gain but theorically, the gain loop which is l20log(Vb/Va) will decrease if i only enhance the gain of the error amlifier.
imar said:hi freinds!
i found some problems duriny=t the design of a Low Dropout Regulator:
this regulator should have: Vdropout:0.5V, so with Vin 3.3V , Vout must be 2.8V.
the load resisttance goes from 28Ω to 2.8KΩ. the Load capacitor is 2.2µF
this regulator has : * a PMOS pass element W=6µ/L=1µ.
* Error amplifier with 60 dB
* bandgap 1.2V
* a frequency compensation scheme
thanks in advance for any response that may help me!
imar said:thanks these new specifications
i am new in designing LDOs and i am trying to understand diffrent points that interfer in this kind of design.
so you said that i should specify a range for the input which is Vdd (Vin).and this point wasn't so clear before.that's why i should use two different voltage sources one for the alimentation of the error amplifier and an other voltage source that will be variable. the question is : how could i fixe this range?
another point: i tried first to maintain the stability for different load resistance value (different load current) for 3.3 V Vin, what should i do now? do i need to run a trans simulation or vary the Vin and watch the ac response?
thanks
imar said:hi freinds!
i found some problems duriny=t the design of a Low Dropout Regulator:
this regulator should have: Vdropout:0.5V, so with Vin 3.3V , Vout must be 2.8V.
the load resisttance goes from 28Ω to 2.8KΩ. the Load capacitor is 2.2µF
this regulator has : * a PMOS pass element W=6µ/L=1µ.
* Error amplifier with 60 dB
* bandgap 1.2V
* a frequency compensation scheme
i designed each element apart, and i verified the functionnality of it.
But, when i reessemble the circuit, the circuit goes nice with load resistance of only 2.3KΩ to 2.8KΩ ( current about 1 to 20 mA approximatly).Ifound that Vout is 2.8V and the stability is about 50° as phase margen.
However, if the Rload falls to 1KΩ or less the regulator ceases to work; infact Vout become 3.8V (which means, i think, (Vin)3.3V + (Vdropout)0.5 V) and the circuit is not stable.
is it about the pass element or some thing else?
thanks in advance for any response that may help me!
imar said:thanks !
first, the pass element hasn't w egal to 6µ but 6m and i rectified it before. it was a taping mistake.
second, THanks Ashish: i have designed my LDO each element seperatly and i fixed the pass element size to W/L to supporte a 100mA to 6m/1µ.
then i designed the error amplifier to have 60 dB dc gain and i used a compenation scheme that i mentioned before.
i have a question: i read that LDO could generate different value of output voltages.is rhat true?
you will find joined a kind of spec. could you explain me what does it mean especially the ranges of Vin and Vout?
how could i achieve a PSRR simulation in Cadenec and how could i found the quiescent current?
thanks a lot for yr help.
Added after 3 minutes:
imar said:thanks for all these information!
let's look now to another point, when i tried to simulate the dc open loop gain with AC simulation for different Rload values the phase alternate its origine and when i reduce RLOAD , it begun from 180° and not from 0°, which means that inputs V+ and V- of the error amplifier are not stable?
how can i manage to resolve with this problem?
imar said:1/2- for the AC analysis, i meant the loop gain but the term 'open' was added to show that this simulation was runned with an open loop.
3- to have a stable system the phase margen us calculating referring to 180°. so i think that the phase has to begin from 0. if it is not the phase margen could be around several degrees 100° or even more as the corves shown.
4- concerning inputs, you have right. i only want to say that V+ and V- alternate and not a stability issue of inputs.
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