Problem with Layout
Hi,
You’re welcome. But, I haven’t been able to find out the operation of the circuit. I think the gates of transistors MN2, MN7 and MN8 (which are connected together) are floating and not controlled by any node, while they should be connected to either a source or drain of another transistor or input node to be controlled. The same thing is for the gates of transistors MN1, MN9 and MN10.
By the way, I think you can replace PMOS transistors with NMOS and NMOS transistors with PMOS to do the same operation, because the bulks of all PMOS transistors in the current circuit are connected to the same node (Vdd) while those of NMOS transistors are connected to different nodes. As a result, if you use PMOS transistors instead of NMOS you can have different wells with different potentials.
OpAmp