Problem with layout and LVS report

[ranair123]

I am trying to implement a sum-product block as shown given in
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When I did the layout of the whole circuit, and run the LVS check, I get a short circuit between GND, VbxF, VbyF. But looking at the circuit, there is no connection between VbxF and VbyF and GND. I am not sure why I am getting such an error. It is not wrong to have 3 different Nwells isnt it?

The layout and the lvs report are here
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I am using Mentor Graphics IC Station for this.

Can anyone help me out with this problem?

Thanks in Advance,
ranair123

 

[OpAmp]

Problem with Layout

I think you are using a N-well process. So, all NMOS transistors are in p-substrate. Since there is just one substrate, VbxF , VbyF and GND are all connected to substrate, therefore connected together. If you use a twin-well process then you can use different P-wells and have no connection between VbxF, VbyF and GND.

 

[ranair123]

Re: Problem with Layout

BULLS EYE !!!!!

That is the exact problem, I didnt realise it (infact I didnt even think in those lines) till you pointed it out. I am using an n-well process and not a twin-tub process. What do you think can be the workaround? Using PMOS instead of NMOS to perform the same operation would help me?

Thanks a lot !!!

 

[OpAmp]

Problem with Layout

Hi,

You’re welcome. But, I haven’t been able to find out the operation of the circuit. I think the gates of transistors MN2, MN7 and MN8 (which are connected together) are floating and not controlled by any node, while they should be connected to either a source or drain of another transistor or input node to be controlled. The same thing is for the gates of transistors MN1, MN9 and MN10.
By the way, I think you can replace PMOS transistors with NMOS and NMOS transistors with PMOS to do the same operation, because the bulks of all PMOS transistors in the current circuit are connected to the same node (Vdd) while those of NMOS transistors are connected to different nodes. As a result, if you use PMOS transistors instead of NMOS you can have different wells with different potentials.

OpAmp