ombadei
Member level 3
uso de variables en vhdl
Ok.. I am a bit confused now.. is this dependent on the tool that is used?
So, what about this situation where a and b are signals in the below code and clkin is a free running clock?
Ok.. I am a bit confused now.. is this dependent on the tool that is used?
So, what about this situation where a and b are signals in the below code and clkin is a free running clock?
Code:
process (clkin)
begin
a <= b;
end process;