nicx82
Newbie level 2
Hello,
i have an entity with 38 bidirectional lines (IO). I have a process that initialize a temporary signal (st_logic-vector) to Z (so i have 38 Z):
IOtemp<=ZZZZZZZ...;
When a control signal goes to '1' this temporary signal is filled with 1 or 0 in precise positions (so i have this 38 lines signal with some 0, some 1 and others line with Z). eg;
IOtemp<=ZZ1Z01Z......;
After filling the IOtemp signal, this IOtemp signal is copied to bidirectional lines:
IO<=IOtemp;
but if i simulate the .vho file from Quartus in my ActiveHDL project the line that must be Z (high impedance) are 0 or 1 and the others lines are correct.
Why?
Please help me. Thanks
Nick
i have an entity with 38 bidirectional lines (IO). I have a process that initialize a temporary signal (st_logic-vector) to Z (so i have 38 Z):
IOtemp<=ZZZZZZZ...;
When a control signal goes to '1' this temporary signal is filled with 1 or 0 in precise positions (so i have this 38 lines signal with some 0, some 1 and others line with Z). eg;
IOtemp<=ZZ1Z01Z......;
After filling the IOtemp signal, this IOtemp signal is copied to bidirectional lines:
IO<=IOtemp;
but if i simulate the .vho file from Quartus in my ActiveHDL project the line that must be Z (high impedance) are 0 or 1 and the others lines are correct.
Why?
Please help me. Thanks
Nick