PROBLEM WITH HIGH INMPEDANCE AND QUARTUS ii

[nicx82]

Hello,
i have an entity with 38 bidirectional lines (IO). I have a process that initialize a temporary signal (st_logic-vector) to Z (so i have 38 Z):
IOtemp<=ZZZZZZZ...;

When a control signal goes to '1' this temporary signal is filled with 1 or 0 in precise positions (so i have this 38 lines signal with some 0, some 1 and others line with Z). eg;

IOtemp<=ZZ1Z01Z......;

After filling the IOtemp signal, this IOtemp signal is copied to bidirectional lines:

IO<=IOtemp;

but if i simulate the .vho file from Quartus in my ActiveHDL project the line that must be Z (high impedance) are 0 or 1 and the others lines are correct.

Why?

Please help me. Thanks
Nick

 

[FvM]

PROBLEM WITH HIGH INMPEDANCE AND qu(at)rtus ii

'Z' is a defined STD_LOGIC value, but it can't be represented by a registered signal. You didn't mention the actual type of the temporary signal, but a wire signal, that directly drives the IO-pin, usually can forward the 'Z' state. A wire, even if it's passed through the design hierarchies, is nothing but an alias of IO pin, so if you set 'Z' to the wire signal somewhere in the design, you actually operate the pins' three-state driver. But registering the signal won't work.

 

[nicx82]

Thanks for the reply. All signal are std_logic_vector