Problem with frequency pushing in VCO

[khorlipmin]

My VCO performed badly for frequency pushing. I wonder if I had tested it in the wrong way. hope someone can help out. The differential current controled oscillator uses triple feedback. I tested it with a current sourse at the NMOS bias current and the PMOS load is controlled by a control voltage. The question is when I vary the supply voltage, should the supply voltage to the current source and the control voltage changes as well? When I have all these parameters changed, the slope is around 300MHz/V, if only the supply voltage changes independently, the figure doubled.
I am thinking that I should include the replica biasing circuit before I test it for frequency pushing, as when the supply voltage goes up, the biasing current will decrease which is the opposite case of a CCO core test with independent current source.
Thanks

 

[khorlipmin]

Re: frequency pushing

I realised that I am able to either obtain a high voltage swing or a very low voltage swing at the output depending on the NMOS differential pair operational region. Does this affect the supply voltage sensitivity?
I get less with the NMOS in saturation but the amplitude is less than a volt and it is around 2.5V to 3V. Should it be at the lower voltage level instead? i.e. 0 to 1 V? how do I buffer it for full swing?
Most importantly shound I make the NMOS operation in full switching or just saturation?
thanks

please find the delay buffer diagram at

 

[laglead]

Re: frequency pushing

1. I think NMOS bias voltage is derived from constant bias current and does not have relationship with supply voltage. The only voltage you should adjust is VCO cell's supply voltage.

2. It is not practical to make swing between 0 and 1v. You should increase swing as large as possible unless your frequency goal cannot be met. Keeping input NMOS in saturation is not a good choice, because this will limit swing between e.g. 2.5v to 3v. This range is not favorable for MC to work. Try sizing MC to enlarge swing may be a good choice. Input NMOS sizing will affect load.

3. Choice of buffer circuit depends on differential or single -ended output.
For single-ended output you can use two NMOS as two inputs and two PMOS as load. One PMOS is in diode-connected style and mirrors signal of one side to the other.