Problem with downloading code on FPGA using Vertix

[Naz]

I am using Xess SV board V1.1, using Parallel Port.I am getting an eroor "cable connection failed "When trying to download via ISE . On using GXLOAD I am getting an error again . How should I download my code on the FPGA?How can be change the direction of Parallel Port ,making it unidirection?

 

[bibo1978]

Re: PROBLEM WITH VERTIX

I am not sure but I guess XESS always uses a CPLD to manage the interface between the FPGA and the parallel port, if so in your kit is the case, check that the appropriate confiiguration of the CPLD is on it usually the code comes with the kit, may be this help

 

[yego]

Re: PROBLEM WITH VERTIX

If you use the ISE WebPack, it is likely that applying the most recent patches will solve the problem. The iMPACT package in some versions had a bug, which Xilinx used to patch in every new release.