sachinmaheshwari
Member level 4
i want to go till GDSII
i have my code simulated using ncverilog
and i have also synthesized it using RC compiler
so after compiling i have .sdc and .v file
now i have to do place n route using SOC ENCOUNTER
i have the manual and all the reading material but still facing some problem
the libraries i have used is
UMC
both for iopads and standard cell
25C and 1.8V(temperature and voltage)
so, in SOC Encounter i impoterd the design but i am getting the iopins(the core area) but not the iopads (area outside the core area)
so what is the problem?
i have my code simulated using ncverilog
and i have also synthesized it using RC compiler
so after compiling i have .sdc and .v file
now i have to do place n route using SOC ENCOUNTER
i have the manual and all the reading material but still facing some problem
the libraries i have used is
UMC
both for iopads and standard cell
25C and 1.8V(temperature and voltage)
so, in SOC Encounter i impoterd the design but i am getting the iopins(the core area) but not the iopads (area outside the core area)
so what is the problem?