Problem with doing place and route using SOC Encounter

[sachinmaheshwari]

i want to go till GDSII
i have my code simulated using ncverilog
and i have also synthesized it using RC compiler
so after compiling i have .sdc and .v file
now i have to do place n route using SOC ENCOUNTER
i have the manual and all the reading material but still facing some problem
the libraries i have used is
UMC
both for iopads and standard cell
25C and 1.8V(temperature and voltage)
so, in SOC Encounter i impoterd the design but i am getting the iopins(the core area) but not the iopads (area outside the core area)
so what is the problem?

 

[snr_vlsi]

Re: SOC Encounter

Hi,

First of all tell me whether ur design is a full chip or block.

Have you loaded the .io assignment file which contains the info. about pads like orientation, offset, and other info. Have you loaded the libraries correctly and in correct sequence.

check this first

thx

snr_vlsi

 

[sachin maheshwari]

Re: SOC Encounter

i have implemented a synchronous up-down counter with load, reset and mode pins.
so i want to see its GDSII format,but i got stuck at encounter(cadence)
so before importing the design to SOC Encounter i have synthesized and generated .sdc and .v files only.

u was saying about .io file so its is generated before placement and floorplanning
while doing synthesis.
reply

 

[arunragavan]

Re: SOC Encounter

Do you stiched your IO pads to your netlist..Do u have the pad instances in the netlsit?

Thanks

 

[vlsitechnology]

SOC Encounter

If the design is a block level then io assignment file contains the io pin information....It doesn't mean that io assignment file should contain only io pads information like orientation, offset and pad location information............

I request u to plz check ur files which ur importing

Hope it is clear to u

Bye take care