Problem with CLK in DCM: the signal is not getting locked

[sanjana]

clkx2 dcm

I have a problem with generating CLK2X(twice the frequency) in virtex II FPGA .I am using the on chip DCM.My problem is when I am simulating using modelsim,the signal is not getting locked.so I am not getting The output clock.could any one please help me with the configuration file and the program needed to generate CLK2X.

 

[sree205]

feedback on dcm ucf

I'm not sure about this method. but, if u r using verilog, can u generate an internal clock which is the not of the clock you are using and try to have the signal change using posedge of either the global or the local clock ? this might solve the issue without going to the DCM at all.

 

[ilikebbs]

CLK in DCM

How about your simulation time?
DCM need very long time to indicate locked.

 

[sanjana]

Re: CLK in DCM

I have given enough time for simulation.Is there any particular reason why it doesn't get locked.

 

[BuBEE]

CLK in DCM

You used CoreGEN Or code Template in ISE ?

 

[yeewang]

CLK in DCM

see if your input clock frequency sits the acceptable range of DCM.

 

[sanjana]

Re: CLK in DCM

I used the installation template for using the DCM.and I had the clock in the frequency range specified.Has anyone got the code thats working.

 

[goshahar]

Re: CLK in DCM

Hi

i have a working design in xilinx virtex2 pro with 3 clocks one of them is clkx2.

the instance:

#dcm_x2 dcm_x2(
// Outputs
.CLK0_OUT (clk_0),
.CLK180_OUT (clk_180),
.CLK2X_OUT (clkx2),
// Inputs
.CLKIN_IN (clki)) ;

Attributes for DCM, blkname = DCM_INST
CLK_FEEDBACK = 1X
CLKDV_DIVIDE = 2
CLKFX_DIVIDE = 1
CLKFX_MULTIPLY = 4
CLKIN_DIVIDE_BY_2 = FALSE
CLKIN_PERIOD = 40
CLKOUT_PHASE_SHIFT = NONE
DESKEW_ADJUST = SYSTEM_SYNCHRONOUS
DFS_FREQUENCY_MODE = LOW
DLL_FREQUENCY_MODE = LOW
DUTY_CYCLE_CORRECTION = TRUE
FACTORY_JF = 16'hC080
PHASE_SHIFT = 0
STARTUP_WAIT = FALSE

i dont know what more do you need so let me know and i may be able to create and test on my device a dcm with clkx2

 

[Ethelthefrog]

Re: CLK in DCM

You have selected feedback as "1X" but you haven't connected the CLKFB pin. Check the user manual for details.

In short, take CLK0 to a BUFG, then route the output of that BUFG back to CLKFB.

 

[goshahar]

Re: CLK in DCM

hi Ethelthefrog

the clkfb is not wired becase i chose internal feedback.
the connection between clkfb and clk0 was made inside the verilog code of the dcm i sent.
you are abolutely right and there should be an internal feedback, but since i chose internal feedback then you dont have to add it to the instance declaration.

thanks

 

[sanjana]

Re: CLK in DCM

thanks ur verilog verrsion is working.But it needs to have the libarary unisim included in the verilog file .I don't know how to do that. I am trying with the VHDL code but even with the sane parameters it is not getting locked.so please help me regarding this

 

[goshahar]

Re: CLK in DCM

hi sanjana,

I dont know exactly what you did that didnt work, you should know i created the dcm for synopsys DC FPGA. This is what i am doing to make it work:

1) copy the instance of the dcm to the top :
#dcm_x2 dcm_x2(
// Outputs
.CLK0_OUT (clk_0),
.CLK180_OUT (clk_180),
.CLK2X_OUT (clkx2),
// Inputs
.CLKIN_IN (clki)) ;

2) synthesize the modules and the dcm.v .
the dcm sould be black box at the end of the synthesis.

3)put all 3 file i gave you in the folder that the ISE tool is using for the p&r.

4) copy the ucf constraints of the dcm from the ucf file i gave you to the ucf file of your design.

5) now run P&R.

good luck

and keep me posted if you need any thing else

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