mmarco76
Member level 5
Hi all, I've discovered only today this forum and hope someone can help me (I've also search in it but not found any answer to my question).
I'm implementing a ATSC compliant trasmitter with an FPGA.
I've done it also with the Matlab.
I can compare my FPGA output with matlab simulation and all is ok but I've a receiver that DON'T lock (tell me that FEC unlock).
I've seen a lot of strange things and I've some question.
The strange thing is that I can see the constellation but seems that I've all the simbol inverted (obviously I've tried to invert them at the source but without any result).
I think that my problem could be in the Trellis Encoder implementation cause the specification seems to me a bit dark..
Now let's start the questions:
1- In the specification of ATSC seems that in each Trellis Encoder and Decoder D is 12 bit retards, but if I watch at Ungerback D= 1 bit only.
(I've implemented it in all the 2 way and I'm quite sure that D=1 is the correct one, and the D=12 symbols in the specifications refers to the fact that each trellis is selected once in a 12 symbols cycle.. sorry for the english I hope it's understandable)
Someone can confirm it to me please?
2- Sync question and trellis:
On the specification is reported that "Allowing for segment sync to input to 4 encoders is skypped but the encoders cycle with no input"!
What the hell does it mean?
It means that I've to send a couple of bit equal to 00 (zero) when I've the sync or that simply the encoder is skypped?
I've understood the mechanism of the 12 Mux and Decode at the beginning and end of the trellis, so I know what to do with the selection of the trellis at the data field boundaries (corresponding to when there is the sync).
3- Trellis Syncronization.
Trellis is never resetted right? I mean it's internal state are no resetted in correspondance of each Frame, right?
I've also searched the forum for seen if someone has a simulation of the trellis or simply an output of it.
I've simulated trellis with a counter at his entrance and also with a series of mpeg null packet (0x47 followed by all 0x0 for).
Hope someone can help me cause on google and in all specifications/doc I've read the only trellis information are not clarifying my doubts.
Added after 4 hours 36 minutes:
None can help me?
I'm convincing that in the specification D=12 symbols delay means that, If I enable each mux only once every 12 symbols, D is a single bit delay.
In that case when there is the Segment Sync I've only to advance my input mux of 4 positions and not to insert the couple of bits = 00.
Question 3 is been open.
Moreover I see that on the constellation if I remove a symbol (such as if I map the -1 into +1, I expect to find a constellation in which -1 symbol is not showing) I find that the symbols are inverted (instead of finding -1 missing I see that the +1 is missing!!!).
It'll be very usefull to have the stream just before the pilot insertion and VSB modulation, if someone can provide it to me just to compare with my 3bit symbols in that point.
So I need the stream in input and the one in output to the Trellis.
Thx
I'm implementing a ATSC compliant trasmitter with an FPGA.
I've done it also with the Matlab.
I can compare my FPGA output with matlab simulation and all is ok but I've a receiver that DON'T lock (tell me that FEC unlock).
I've seen a lot of strange things and I've some question.
The strange thing is that I can see the constellation but seems that I've all the simbol inverted (obviously I've tried to invert them at the source but without any result).
I think that my problem could be in the Trellis Encoder implementation cause the specification seems to me a bit dark..
Now let's start the questions:
1- In the specification of ATSC seems that in each Trellis Encoder and Decoder D is 12 bit retards, but if I watch at Ungerback D= 1 bit only.
(I've implemented it in all the 2 way and I'm quite sure that D=1 is the correct one, and the D=12 symbols in the specifications refers to the fact that each trellis is selected once in a 12 symbols cycle.. sorry for the english I hope it's understandable)
Someone can confirm it to me please?
2- Sync question and trellis:
On the specification is reported that "Allowing for segment sync to input to 4 encoders is skypped but the encoders cycle with no input"!
What the hell does it mean?
It means that I've to send a couple of bit equal to 00 (zero) when I've the sync or that simply the encoder is skypped?
I've understood the mechanism of the 12 Mux and Decode at the beginning and end of the trellis, so I know what to do with the selection of the trellis at the data field boundaries (corresponding to when there is the sync).
3- Trellis Syncronization.
Trellis is never resetted right? I mean it's internal state are no resetted in correspondance of each Frame, right?
I've also searched the forum for seen if someone has a simulation of the trellis or simply an output of it.
I've simulated trellis with a counter at his entrance and also with a series of mpeg null packet (0x47 followed by all 0x0 for).
Hope someone can help me cause on google and in all specifications/doc I've read the only trellis information are not clarifying my doubts.
Added after 4 hours 36 minutes:
None can help me?
I'm convincing that in the specification D=12 symbols delay means that, If I enable each mux only once every 12 symbols, D is a single bit delay.
In that case when there is the Segment Sync I've only to advance my input mux of 4 positions and not to insert the couple of bits = 00.
Question 3 is been open.
Moreover I see that on the constellation if I remove a symbol (such as if I map the -1 into +1, I expect to find a constellation in which -1 symbol is not showing) I find that the symbols are inverted (instead of finding -1 missing I see that the +1 is missing!!!).
It'll be very usefull to have the stream just before the pilot insertion and VSB modulation, if someone can provide it to me just to compare with my 3bit symbols in that point.
So I need the stream in input and the one in output to the Trellis.
Thx