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[SOLVED] PHY to MAC communication: issue with SMI (MDIO+MDC) bus

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Lucast85

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Hi everyone,

I've designed an embedded board with a SOM module based on STM32MP153 microcontroller and a PHY transceiver from ADI, the ADIN1200. The connections between the two devices are the followings (from AN5031 - STM):
ETH_PHY_connections.png


I've some issues when I try to communicate with the PHY ADIN 1200.
For example, when I try to read from the read-only register 0x03 (Manufacturer Model nr, etc.), I read different values each time I try to read it. Sometimes the information is correct because I read 0xBC20, other times is very different (e.g. D07F, 9E08, 1000, etc.) and has no-sense.
I thought the PHY is not able to understand the read request received from the MAC of STM32MP1 and it send back the random content of some other registers. However, if I try to ask the content of the register 0x03 of the PHY 0x01, that not exist because the only PHY has address 0x00, no one responds (that is correct). From this experiment it seems that the PHY is able to understand the request from the MAC (at least in the first part, that cointains the PHY address). I thought it could understand also the following part cointainind the register's content.

The signals, measured close to the PHY is the following:
read_0x03_MDIO.png

From this image,
  • B marker is at the end of the 32 bit preable;
  • b is the marker at the end of the reg. address (0b00011);
  • the 1 bit on the MDIO on the right side of the screen is the response from the PHY (that is not obviously 0xBC08);
I've some overshoot that is possible adjust by tunign the 22R series resistor on MDC (clock) but I've not any symilar resistor on MDIO line. However, I know the signals are sampled far away from the "ringing phase"...
What could I do to investigate on this issue?
Thank you in advance.
 

Lucast85

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Solved!
Despite, from the block diagram, the MDIO control block seems to be a stand-alone part of the IC, to work properly, it is mandatory to provide the 50MHz ext clock to the IC.
The power-up timing figure 2 highlight the presence of the external clock in the inital phase.
 

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