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[SOLVED] problem with 2 terminal resistor

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polygon pusher

Newbie level 5
Sep 15, 2010
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I have a 2 terminal resistor placed in the schematic which has it's bulk connected to sub! (I can't see how it is set in the menu!)
The resistor is placed as a tie low with one end connected to vss.

When I lay it out the LVS complains that my Sub! is shorted to vss. Is there anyway to set the 2 terminal resistors bulk to be tied to vss in the schematic to stop the error occuring??

I am using Cadence schematic and Layout XL


there are a few unknown terms: 2-terminal resistor, bulk, sub, tie, LVS :-o could you please come again.

Note: I am not sure whether it is only me who is not aware of these terms :???: pls ignore in that case.
From the terms you use i suppose you work with an IBM pdk.Right?Under this assumption,you correctly connect the third (middle) terminal of the resistor to sub!.(What do you mean by saying I can't see how it is set in the menu! ?).Do you have subc device in your schematic and layout?I suspect that the problem is there.

Please give me a snapshot of the schematic & layout of the resistor and a snapshot of the exact LVS error.

A final remark : When you ask for such kind of solutions you should always say the CAD tool version,the pdk's fab and version,the device type that has the problem (e.g. mimcap) and if possible give screenshots with the problem to appear clearly.Only in this way you will get a detailed and direct answer.
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One more thing you can check is the type of symbol being used in schematic for the resistor.
If its a 2 terminal symbol or three terminal symbol.

For 2 terminal symbol you can enter the sub terminal name in form itself, while in 3 terminal symbol ( like symbol3T ) you can add extra wire in schematic for substrate node and connect to required substrate potential.

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