Problem measuring two waves phase shift with 4046 Phase Comparator II

[^saint^]

Hi, in my project i have two sin waves (few Hz to about 2kHz) that are 90 deg out of phase (TLL levels). What I need to do is determine if wave A is currently leading or trailing wave B so naturally after using LM393 I wanted to use 4046B and its Phase Comparator II output. Wave A goes to pin 14, and B to pin 3 of 4046. At pin 13 i put resistor divider (1M + 2k/2k) as suggested here but I'm pretty sure it should be the other way around eg. 10k + 1M/1M) so that the 1M can actually pull the output close to VCC or GND.
But no matter what I do the PC2 doesn't stay an VCC/2 when Wave A & B are at VCC/2 (DC), sometimes PC2 sticks to VCC sometimes to GND and occasionally I see VCC/2 (on PC2) when generating Wave A & B. What am I doing wrong?

Resistor divider used for measurments is 10k + 1M/1M.
SIG (ch. 1) and COMP (ch. 2)


From separate measurment, PCP (1), PC2 (2)


One more thing is that PCP is Low when SIG & COMP are VCC/2, according to the datasheet (page 8) it should be High. Any ideas why?

Everything was tested with my Rigol oscilloscope (only 2-ch. :-() and the singnals on pin 3 & 14 are clean (not exactly 50% duty but this doesn't matter for PC2 as far as I know).

Do I need to connect C1, C2, R1,R2, RS, looking at the datasheet (page 4, fig. 2) I don't
think I'm using any of them.

What should one do with unused pins on 4046, leave them floating?

 

[chuckey]

" that are 90 deg out of phase ", then you say " if wave A is currently leading or trailing wave B " . So you know that they are 90 degrees out of phase but you don't know which one is leading?
That IC is too complicated for me!, shame they have not got a typical circuit.
The way I would do it is , put both signals through a divide by two, now you have two square waves. Put them as inputs to an EXOR gate, this will give a string of pulses with a DC mean equal to the phase shift ( 0 - 90 Degs). Use one square wave to drive a short period mono stable (50 microsecs?) and use this to gate the other square wave, if the rising edge of SW1 is sampling SW2, then it will give an output of a string of pulses is SW2 is a 1 or stay at zero if SW2 is a 0.
Frank

 

[crutschow]

That data sheet I looked at loaded the PCII output with 20k and 2k/2k not 1meg and 2k/2k.

The PCII comparator is a digital logic circuit with memory that looks only at the rising edges of the input pulse. When the two input signal edges are exactly in phase then you get no output. If the two are not in phase then the output goes high or low (depending upon the relative phase) for the time period between the two rising edges. I believe that is what you are seeing.

So to determine the relative phase direction of the two signals you just need to look at the average output voltage of PCII.

Generally you connect unused input (not output) CMOS pins to Vcc or ground.

 

[KlausST]

Hi,

Use a D flipflop.
Put one signal on the clock of the DFF,
Put the other to the D input of the DFF.

The output of the DFF tells you whether it is leading or trailing

Klaus

 

[betwixt]

Everyone is right!
Use a D flip-flop as Klaus suggests to determine whether it is leading or lagging the reference signal and also connect the two signals to an XOR gate to determine the relative phase difference as Frank suggests. It should work from near DC to 10s of MHz using this method.

Brian.

 

[^saint^]

" that are 90 deg out of phase ", then you say " if wave A is currently leading or trailing wave B " . So you know that they are 90 degrees out of phase but you don't know which one is leading?

Exactly

That data sheet I looked at loaded the PCII output with 20k and 2k/2k not 1meg and 2k/2k.

It might but I don't think it is correct, it should be the other way around or the change at PC2 will be very small. Parallel connected resistors 20k with 2k won't will still give a Rs close to 2k (when it's PC2 -> 20k -> 2k/2k), so instead it should be PC2 -> 2k -> 20k/20k or better yet PC2 -> 20k -> 1M/1M so it won't source too much current from PC2.

Use a D flipflop.
Put one signal on the clock of the DFF,
Put the other to the D input of the DFF

Will try this as I've seen someone using a dual D flip-flop for this.

Everyone is right!
Use a D flip-flop as Klaus suggests to determine whether it is leading or lagging the reference signal and also connect the two signals to an XOR gate to determine the relative phase difference as Frank suggests. It should work from near DC to 10s of MHz using this method.
Brian.

Isn't this exactly the same as PCP output of 4046? The only difference is they are using a bunch of NOT gates but I'm guessing it's just for amplifying the current.

 

[schmitt trigger]

The phase pulses output indicates whether there is a phase difference or not. The main PC II output will, as Crutschow indicated, whether it is leading or lagging.

 

[^saint^]

The phase pulses output indicates whether there is a phase difference or not. The main PC II output will, as Crutschow indicated, whether it is leading or lagging.

I've got that. I was simply interested what those NOT gates are doing in PCP.

I'd swing by a local shop a bought a few parts (CD4013B, 74LS86). This is what I get from Q output and XOR:


Not exactly what I was hoping for.

 

[^saint^]

Sorry can't edit my last post.

I've used my sniffer. Wave A goes to input D of flip-flop, B goes to CLK.

#1


#2


#3


Any ideas how to make XOR only work on leading edge?

 

[betwixt]

I don't think you need to. The XOR output is high when the phase of the signals means they are not overlapping. You need to take the mean voltage (try an RC network) which is proportional to their phase difference rather than use the instantaneous logic output.

Brian.

 

[crutschow]

An XOR can tell you the phase difference but it cannot tell which input is leading and which is lagging just my looking at its output. The FF based phase-detectors can.

 

[Borber]

Use 74*74 and connect D and CK to signals. Q output will show you which signal is leading or lagging. Similar circuit is used with rotary encoder to indicate the direction of rotation.

 

[^saint^]

You need to take the mean voltage (try an RC network) which is proportional to their phase difference rather than use the instantaneous logic output.
Brian.

The problem is that after putting sin waves A and B through a comparator the square waves aren't shifted 1/4 of HIGH-state (the waves change amplitudes but when they are present).

An XOR can tell you the phase difference but it cannot tell which input is leading and which is lagging just my looking at its output. The FF based phase-detectors can.

This is all fine the only problem is that the sin/square waves arent always present, the problem is that if you look at #1 the consecutive XOR high states are actually for one pair of A,B high pulses. Sampling Q at both consecutive Hi states will actually gave a false resoult as Lead + Lag when in fact only the first is true.

Use 74*74 and connect D and CK to signals. Q output will show you which signal is leading or lagging.

This has already been suggested the only problem is knowing when to sample Q output as the A and B waves arent always present and the XOR is triggered twice with each A,B pair.

 

[D.A.(Tony)Stewart]

Saint , You will get much better answers if you provide details on the performance you are trying to control and the level of signal and noise present. Also read the Chip spec again on the detector features, your understanding is missing a lot of details.

XOR detector is for perfect sine waves converted to 50% square waves with no noise and is less sensitive to glitches.


If you are trying to use two external sine waves ( like an LVDT) then use a self-biased AC coupled inverter or inverting gate to convert to square wave for Comp_in.

The Type II PC2_out_13 is a tri-state Phase and frequency detector. Pumps up or down according to signal edges only and will be in tri-state mode (V/2 when locked on or synchronous. Be sure which edge is active, also duty cycle does not matter. However if there are missing pulses or extra pulses on the input SIgnal, errors will occur so SNR is not perfect.

A D FF is a subset of the Type II detector or simply a primitive edge detector that only works +/- 90 deg using 1 edge to sample the state of the other signal if early or late and does not work well with different frequencies.

What is your App? Noise level & how often? Do you use the PLL mode?

 

[^saint^]

What is your App? Noise level & how often? Do you use the PLL mode?

**broken link removed** for the module I'm working with it's a doppler radar, **broken link removed** explaining the circuit (Fig. 3 - my simple comparator, 5 & 6). I'm trying to determine which of the I/Q sine waves is leading. The problem is that gain of op amps is fixed but as the object approaches the amplitude of of I/Q increases so does the duty from comparator(s). The frequency is proportional to object speed.

 

[^saint^]

Finally it's starting to work as it should. Used dual 2 stage op amps with total gain of x330. After that a non inverting simple comparator with hysteresis (Low Threshold: 2.8V, High Threshold: 3.2V) so it only outputs high when the sine wave has sufficient amplitude an when the signals are in DC (VCC/2) it outputs constant low. Then they go to D flip-flop (wave A -> D input, B -> CLK) and also to XOR.
Here you can see how it works with an approaching object:

Still few false peaks on wave B :sad:

For receding one:

Next I'm gonna try to use AGC on the first stage (VCR FET based probably) to avoid clipping the sine wave.

 

[D.A.(Tony)Stewart]

The comparator symmetry is critical to good phase detection in converting sine to square. Hysteresis adds asymmetry (not good ) but filters low signals (good).

So there are three functions to focus on.

1. Matching your receiver filter bandwidth to match the signal content and thus maximize SNR.
2. Make the Sine signal constant to avoid shift in edges from asymmetry using wide range AGC ( 60dB?)
3. Make Comparator noise free slice at 50% of sine p-p with low error <1%? and not >10% phase error. This requires linear amplification, low offset voltage and speed >50x than signal bandwidth.

Then use another comparator for AGC voltage to disable signal or indicate noisy level. SOme applications use SNR or AGC level to reduce PLL bandwidth, so there is less jitter. but more tracking error.. It is a compromise that can be tweaked with above 1,2,3

 

[^saint^]

1. Matching your receiver filter bandwidth to match the signal content and thus maximize SNR.
2. Make the Sine signal constant to avoid shift in edges from asymmetry using wide range AGC ( 60dB?)
3. Make Comparator noise free slice at 50% of sine p-p with low error <1%? and not >10% phase error. This requires linear amplification, low offset voltage and speed >50x than signal bandwidth.

1. I'll set it for something like 44Hz-4.4kHz which would correspond to 1-100 km/h; person and car detection.
2. Maybe a AGC 20-40dB + 40dB on second stage?
3. Am I understanding it correctly 50 * 4.4kHz => 220kHz so ~4.5 uS, LM339/393 has 1.3uS Response Time or am I looking at the wrong parameter?

Then use another comparator for AGC voltage to disable signal or indicate noisy level. SOme applications use SNR or AGC level to reduce PLL bandwidth, so there is less jitter. but more tracking error.. It is a compromise that can be tweaked with above 1,2,3

Could you provide an example?

After some more testing of this simple circuit from **broken link removed** I have to say that it's nowhere near claimed 10 m of detection range, plus amplified noise is creating false detection. I've only swapped the LMV774 for a **broken link removed** it's a little bit noisier. Tested with a few amp gains (A1*A2):
reference desing: 22*100, a lot of noise practically unusable
10*100, distance of detecting a person ~3m but some noise is present
33*10, distance ~1.5m with no noise
Tested indoors with nothing between person and the module. So the next step is PSU plus LDO to check if it helps with the noise, if not I'm gonna test a more complex circuit from **broken link removed** they also suggest to turn the module on/off with 2% duty I'm sure it will help but still a lot of noise. Another **broken link removed** it has few equations to use when operating in "pulse mode".

I'm gonna order some more parts (mainly op amps) for testing. Any ideas on which ones to get?
I've also seen similar desing using MC33078 but the Input offset voltage is pretty big. This one TS522/4 looks good.

 

[^saint^]

After some time with this **broken link removed** I have a few questions.

1. Why is there a sine wave on signal (3) C109 hold capacitor in Fig. 2a/b when the sensor already disconnected (sampling switch) is U102D oscillating in some way? Is this subsampling and if so how can one calculate the actual Sensor output frequency (for object speed measurement) in the UC?
2. Above U102D there is a note "fu 5kHz". Does "u" stand for upper? Where does this value come from, I can't seem to find similar op amp configuration?
3. I've managed to find that U102A + R107, R115, C101, C104, R103 is in fact a **broken link removed** they call it Notch Filter. What does it do in this circuit and why 100Hz? 100Hz for fc doesn't seem to make any sens when they want to measure near DC to 2.7kHz (1/2 sampling speed).
4. What is R100 suppose to do? How does it affect U102B?
5. Isn't C107 next to MOSFET a little small to smooth any voltage ripple when drawing extra 35mA from VCC? I guess it all depends on the capacitor on 5V rail (source).

There is also a **broken link removed** maybe this is the way to go.