chaitanya.531
Member level 1
Hey Folks,
plz
Need a little help here with my VHDL code.
I'm new to VHDL so please bear with me.
I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim )
When I run check syntax, the following is displayed:
ERROR:HDLParsers:164 - "C:/Xilinx/r1/rr.vhd" Line 65. parse error, unexpected ROW, expecting OPENPAR or TICK or LSQBRACK
ERROR:HDLParsers:164 - "C:/Xilinx/r1/rr.vhd" Line 143. parse error, unexpected PROCESS, expecting IF
the code is
plz
Need a little help here with my VHDL code.
I'm new to VHDL so please bear with me.
I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim )
When I run check syntax, the following is displayed:
ERROR:HDLParsers:164 - "C:/Xilinx/r1/rr.vhd" Line 65. parse error, unexpected ROW, expecting OPENPAR or TICK or LSQBRACK
ERROR:HDLParsers:164 - "C:/Xilinx/r1/rr.vhd" Line 143. parse error, unexpected PROCESS, expecting IF
the code is
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ram is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; key_rdy : in STD_LOGIC; skey0 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey1 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey2 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey3 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey4 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey5 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey6 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey7 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey8 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey9 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey10 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey11 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey12 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey13 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey14 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey15 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey16 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey17 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey18 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey19 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey20 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey21 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey22 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey23 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey24 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey25 : in STD_LOGIC_VECTOR (31 DOWNTO 0); skey_0 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_1 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_2 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_3 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_4 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_5 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_6 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_7 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_8 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_9 : out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_10: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_11: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_12: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_13: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_14: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_15: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_16: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_17: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_18: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_19: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_20: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_21: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_22: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_23: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_24: out STD_LOGIC_VECTOR (31 DOWNTO 0); skey_25: out STD_LOGIC_VECTOR (31 DOWNTO 0)); end ram; architecture Behavioral of r1 is TYPE s_ram IS ARRAY (0 TO 25) OF STD_LOGIC_VECTOR (31 DOWNTO 0); signal s_arr_tmp: s_ram; begin skey0 => s_arr_tmp(0); skey1 => s_arr_tmp(1); skey2 => s_arr_tmp(2); skey3 => s_arr_tmp(3); skey4 =>s_arr_tmp(4); skey5 => s_arr_tmp(5); skey6 => s_arr_tmp(6); skey7 => s_arr_tmp(7); skey8 => s_arr_tmp(8); skey9 =>s_arr_tmp(9); skey10 => s_arr_tmp(10); skey11 => s_arr_tmp(11); skey12 => s_arr_tmp(12); skey13 => s_arr_tmp(13); skey14 => s_arr_tmp(14); skey15 => s_arr_tmp(15); skey16 => s_arr_tmp(16); skey17 => s_arr_tmp(17); skey18 => s_arr_tmp(18); skey19 => s_arr_tmp(19); skey20 => s_arr_tmp(20); skey21 => s_arr_tmp(21); skey22 => s_arr_tmp(22); skey23 => s_arr_tmp(23); skey24 => s_arr_tmp(24); skey25 => s_arr_tmp(25); PROCESS (clk,clr) BEGIN if (clr='0')then skey_0 <= x"00000000"; skey_1 <=x"00000000"; skey_2 <=x"00000000"; skey_3 <= x"00000000"; skey_4 <=x"00000000"; skey_5 <= x"00000000"; skey_6 <=x"00000000"; skey_7 <=x"00000000"; skey_8 <=x"00000000"; skey_9 <=x"00000000"; skey_10 <=x"00000000"; skey_11 <= x"00000000"; skey_12 <= x"00000000"; skey_13 <=x"00000000"; skey_14 <=x"00000000"; skey_15 <= x"00000000"; skey_16 <=x"00000000"; skey_17 <=x"00000000"; skey_18 <=x"00000000"; skey_19 <=x"00000000"; skey_20 <=x"00000000"; skey_21 <=x"00000000"; skey_22 <=x"00000000"; skey_23 <=x"00000000"; skey_24 <=x"00000000"; skey_25 <= x"00000000"; else if (clr ='1') then IF(clk'EVENT AND clk='1') then if (rising_edge(key_rdy)and (key_rdy ='1')) then skey_0 <= s_arr_tmp(0); skey_1 <= s_arr_tmp(1); skey_2 <= s_arr_tmp(2); skey_3 <= s_arr_tmp(3); skey_4 <= s_arr_tmp(4); skey_5 <= s_arr_tmp(5); skey_6 <= s_arr_tmp(6); skey_7 <= s_arr_tmp(7); skey_8 <= s_arr_tmp(8); skey_9 <= s_arr_tmp(9); skey_10 <= s_arr_tmp(10); skey_11 <= s_arr_tmp(11); skey_12 <= s_arr_tmp(12); skey_13 <= s_arr_tmp(13); skey_14 <= s_arr_tmp(14); skey_15 <= s_arr_tmp(15); skey_16 <= s_arr_tmp(16); skey_17 <= s_arr_tmp(17); skey_18 <= s_arr_tmp(18); skey_19 <= s_arr_tmp(19); skey_20 <= s_arr_tmp(20); skey_21 <= s_arr_tmp(21); skey_22 <= s_arr_tmp(22); skey_23 <= s_arr_tmp(23); skey_24 <= s_arr_tmp(24); skey_25 <= s_arr_tmp(25); end if ; end if ; end process; end Behavioral;
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