problem in verilog code

[priyanka24]

Hi......
me facing problem in my coding.
everything syntax was correct but in simulation output 'o' is getting as 'XXXX' i.e unknown.
so plz tell me what i should do for that???????????
my code is as follows::



module runcount(i, o, addr);
input [7:0] i;
input [3:0]addr;
output [3:0]o;
reg [3:0]o;
integer count=0;
integer j;
reg [3:0] mem_bank [0:7];
always@(i)
begin
for(j=7;j<=0;j=j-1)
begin

if(i[j]==0)
begin
o=o+1;
end
else
begin
mem_bank[addr]=o;
end
end
end
endmodule

 

[golden_star]

Do you have the testbench..?

 

[priyanka24]

Do you have the testbench..?

no.
first we tried to verify it with help of test bench waveform but not getting output.

 

[poluekt]

You must define initial value for reg output 'o' .
For example,
initial o=3'h0;

 

[priyanka24]

You must define initial value for reg output 'o' .
For example,
initial o=3'h0;

in that case output always assigned to 0.

 

[krishna2728]

can u post your test bench here

 

[shanmugaveld]

Output is not initialized to any value.
So it will take XX only.
If you perform any operation with X's you will get x only.
If it is synthesizable code
use one pin to reset the value of registers
else
you can use initial(it will execute only once not always) or the way you have initialized the variable count.

 

[priyanka24]

Output is not initialized to any value.
So it will take XX only.
If you perform any operation with X's you will get x only.
If it is synthesizable code
use one pin to reset the value of registers
else
you can use initial(it will execute only once not always) or the way you have initialized the variable count.

i have tried that by initializing output to '0'. But then output is always coming as zero.
this is code shown below:

module runcount(i, o);
input [7:0] i;
output [3:0]o;
reg [3:0]o;
integer count=0;
integer j;

initial o=4'b0000;
always@(i)
begin
for(j=7;j<=0;j=j-1)
begin

if(i[j]==0)
begin
count=count+1;
end
else
begin
o=count;

count=0;
end
end
end
endmodule


but output always '0' coming. plz help if u can...

---------- Post added at 18:56 ---------- Previous post was at 18:55 ----------

can u post your test bench here

no.first me trying it with simple waveforms.

---------- Post added at 18:57 ---------- Previous post was at 18:56 ----------

You must define initial value for reg output 'o' .
For example,
initial o=3'h0;

here is code where i have assigned '0' to output.but in this case output is always coming as '0'

module runcount(i, o);
input [7:0] i;
output [3:0]o;
reg [3:0]o;
integer count=0;
integer j;

initial o=4'b0000;
always@(i)
begin
for(j=7;j<=0;j=j-1)
begin

if(i[j]==0)
begin
count=count+1;
end
else
begin
o=count;

count=0;
end
end
end
endmodule


plz help me if u can...

 

[Alosevskoy]

Post please the vectors you send to the module, i.e. i = 8'h....(or maybe you can attach waveforms) If the lsb of the vectors is 1 then you will always get count=0 ( your code do that: see the portion of the code where else statements take place).
Are you going to synthesize this code?

 

[priyanka24]

Post please the vectors you send to the module, i.e. i = 8'h....(or maybe you can attach waveforms) If the lsb of the vectors is 1 then you will always get count=0 ( your code do that: see the portion of the code where else statements take place).
Are you going to synthesize this code?

This is thw waveforms am attaching.



yes i want to synthesize this code.but this is just a part of code i want to store this run lengths am calculating to memory but stuck this part itself so not going further...

 

[Alosevskoy]

This code is not synthesizable. Elaborate your design please (synchronous logic or pure combinational logic; function).
You're sending to the module 8'hA4 = 8'h10101000... Let's follow your code.
Enter to always@ block...
Initial values for count and o is 0...
1 iteration of for cycle:
i[7]==1 -> o = count = 0;
count = 0;
2 iteration of for cycle:
i[6]==0 -> count = count + 1 = 1;
o = old_value = 0;
3 iteration of for cycle:
i[5]==1 -> o = count = 0;
count = 0;
4 iteration of for cycle:
i[4]==0 -> count = count + 1 = 1;
o = old_value = 0;
3 iteration of for cycle:
i[3]==1 -> o = count = 1;
count = 0;
2 iteration of for cycle:
i[2]==0 -> count = count + 1 = 1;
o = old_value = 0;
1 iteration of for cycle:
i[1]==0 -> count = count + 1 = 2;
o = old_value = 0;
0 iteration of for cycle:
i[0]==0 -> count = count + 1 = 3;
o = old_value = 0;

So the answer is 0..
----------
Good luck!

 

[priyanka24]

This code is not synthesizable. Elaborate your design please (synchronous logic or pure combinational logic; function).
You're sending to the module 8'hA4 = 8'h10101000... Let's follow your code.
Enter to always@ block...
Initial values for count and o is 0...
1 iteration of for cycle:
i[7]==1 -> o = count = 0;
count = 0;
2 iteration of for cycle:
i[6]==0 -> count = count + 1 = 1;
o = old_value = 0;
3 iteration of for cycle:
i[5]==1 -> o = count = 0;
count = 0;
4 iteration of for cycle:
i[4]==0 -> count = count + 1 = 1;
o = old_value = 0;
3 iteration of for cycle:
i[3]==1 -> o = count = 1;
count = 0;
2 iteration of for cycle:
i[2]==0 -> count = count + 1 = 1;
o = old_value = 0;
1 iteration of for cycle:
i[1]==0 -> count = count + 1 = 2;
o = old_value = 0;
0 iteration of for cycle:
i[0]==0 -> count = count + 1 = 3;
o = old_value = 0;

So the answer is 0..
----------
Good luck!

in 3rd iteration count value is '1' not '0'. how according to you its '0'. because first we assigning old value of count to o and then count assigned to '0'.

 

[Alosevskoy]

Yes, sorry.... The final value is 2... Fix condition for the for loop, i.e for(j=7;j>=0;j=j-1). I've modeled the code and as expected it returns 2 for 8'hA4.
But it's still non-synthesizable code... Do not use for loop in a software manner, think about hardware (comb logic, flip-flops, etc) when you write HDL descriptions.

 

[priyanka24]

Yes, sorry.... The final value is 2... Fix condition for the for loop, i.e for(j=7;j>=0;j=j-1). I've modeled the code and as expected it returns 2 for 8'hA4.
But it's still non-synthesizable code... Do not use for loop in a software manner, think about hardware (comb logic, flip-flops, etc) when you write HDL descriptions.

yes but i dont know the desired components required for it. for that am trying to implement it in behavioral first then will try for structural. but not getting how to do it.

 

[shanmugaveld]

if(i[j]==0)
begin
count=count+1;
end
else
begin
o=count;

count=0; --- remove or comment this part and check. you are assigning count value zero here. It is under for loop. so it is causing the issue
end
end
end
endmodule

 

[priyanka24]

if(i[j]==0)
begin
count=count+1;
end
else
begin
o=count;

count=0; --- remove or comment this part and check. you are assigning count value zero here. It is under for loop. so it is causing the issue
end
end
end
endmodule

that am assigning because after one run length i get i have to count another run length in my sequence so assigning it to zero and before that i have assigned my run length to output 'o' which i have calculated.

 

[shanmugaveld]

Then put outside the "for loop".
In FOR LOOP output will be updated after one complete run.
You cant see the intermediate results.
Since you are assigning the counter value to zero, it overrides the original value.
Even if you initialize the "o" as 1 also, it will give result as zero only

 

[priyanka24]

Then put outside the "for loop".
In FOR LOOP output will be updated after one complete run.
You cant see the intermediate results.
Since you are assigning the counter value to zero, it overrides the original value.
Even if you initialize the "o" as 1 also, it will give result as zero only

how can i assign outside for loop. if i assign it outside then every time i get zero only..