[SOLVED] Problem in Post-layout simulation

[Maithreyi]

Hi all,

I have done pre-layout and post-layout simulations for an analog circuit (using Cadence).

In Pre-layout and Post-layout simulations, voltage levels at all nodes are almost equal but there is difference in currents.

Currents in post-layout simulations are very less compared to the currents in pre-layout simulations.

What might be the reason for difference in currents? Is that due to the metal widths? Do I need to increase the metal widths till?

Can any1 plz help me out of this problem.

Thanks in advance.

 

[erikl]

As you have all the voltage levels, you should see the voltage drop on the connections, isn't it?

 

[dsrinivasrao]

In the post layout simulation you have to use a "config view(i,e av_extracted view)" while using a ADE window..You might me using a schematic view only for both pre and post layout simulation..Also if your Layout is very small e.g take an inverter the extracted capacitor and resistance values are very less and hence the pre and post layout simulation might look same,but if you are doing a big layout there must be different outputs for pre-layout and post-layout simulation..

 

[Maithreyi]

@erikl

S, there are very small voltage drops on connections.

But the current flow is quite different in pre-layout and post-layout simulations even though I maintained sufficient metal width for connections.

---------- Post added at 15:09 ---------- Previous post was at 15:06 ----------

@dsrinivasrao

I have used av_extracted_view itself, where the parasitics gets added for post_layout simulations.

 

[erikl]

... the current flow is quite different in pre-layout and post-layout simulations even though I maintained sufficient metal width for connections.

Which frequency are you using? Parasitic capacitance can increase the current considerably: i ~ 2πfC .

 

[Maithreyi]

I am using 2.4GHz frequency.

To my surprise, I have seen -ve current in some of the paths. What would be the reason?

 

[erikl]

I am using 2.4GHz frequency.
I have seen -ve current in some of the paths. What would be the reason?

Don't know what your -ve means, but if this is your neg. power supply, you should also see this (DC) current from the pos. power supply. The reason could be charging the additional parasitic caps from the pos. supply and de-charging them to the neg. supply.

 

[Maithreyi]

I mean, Current flowing from power supply to ground is negative.