problem in mixer design...

[naveeng]

dear frns...

iam designing mixer in ADS tool..., mixer designing was completed and implemented in ADS....applied RF and LO signals at input side , and it is single gate FET mixer ....

problem lies is that .... i applied gate bias at gate , drain bias at drain of the FET &

RF signal at 5 GHZ is -30dBm

LO signal at 5.002 is 7dBm

the desired out out signal i.e RF-LO = 20 MHz is really very bad...iam getting output power at 20MHz which is -260dBM..

there is no conversion gain for my active mixer...which is impossible...active mixer generally produce gain ....

plzz tell me the ideas or the mistakes that i made in designing ....i really need ur help...plzz reply me as soon as possible..

thanks and regards...

 

[ieropsaltic]

If I understand you correctly, your mixer is not an active one. If you apply one signal at the FET's gate and the other one is applied at the FET's source and the output is taken at the drain, then this mixer is passive as the signal can't have gain. This would result in deteriorated output power. If you want to use an active mixer, perhaps you may want to use Gilbert cell.

 

[naveeng]

first i combined RF and LO signals ... and the combined RF and LO signal i applied to the gate ...this is my design at input side...so mixer is active one...the problem is at the drain side ...i donno how to design IF matching circuit ..i.e at what frequency whether it is at RF or IF ...and filter circuits...remember iam using transmission lines..since the operatin frequency was in GHZ range..

plzz..help me...in this regard...


thanks and regards....

 

[ieropsaltic]

How did you combine the LO and RF signals?

 

[naveeng]

through combiner...i combined two signals i.e RF and LO....

i need ur help in deigning IF matching circuit at drain side..


thanks and regards...

 

[akrcal]

Hi,

U can check whether you have applied DC bias choke at gate and drain bias or not. You will also have to do RF and LO matching to 50 Ohms port.

Regards

 

[naveeng]

yaa i applied gate bias (-0.4 v) and drain bias (2 v ) as per my transistor bias operating point...

i even tried different bias network...but the result was same....i didnot get conversion gain...

plzz... help....

i uploaded my design block diagram and posted in RF, antennas nad optics forum with subject name...*plzz help me in this...* kindly help...

thanks and regards....

 

[akrcal]

You can post the ADS file schematic. May be somewhere you have done mistake.

Regards