win2010
Member level 1
Hi......
I`m designing DVB-T2 using VHDL for my post graduation as a final year project.
I designed upto parity interleaver in BICM, but I finding a difficulty in design of "Bit interlaver". I request you to pls guide me how to design Bit inerleaver part. Interleaver does not have input to output logic/relation and I designed with taking BUFFER to store but which not Synthsizing in Xilinx.
I`m designing DVB-T2 using VHDL for my post graduation as a final year project.
I designed upto parity interleaver in BICM, but I finding a difficulty in design of "Bit interlaver". I request you to pls guide me how to design Bit inerleaver part. Interleaver does not have input to output logic/relation and I designed with taking BUFFER to store but which not Synthsizing in Xilinx.