problem in design DVB-T2 Bit Interleaver.....

[win2010]

Hi......

I`m designing DVB-T2 using VHDL for my post graduation as a final year project.

I designed upto parity interleaver in BICM, but I finding a difficulty in design of "Bit interlaver". I request you to pls guide me how to design Bit inerleaver part. Interleaver does not have input to output logic/relation and I designed with taking BUFFER to store but which not Synthsizing in Xilinx.

 

[TrickyDicky]

The usual response: Post the code.

If there is no outputs from your design, then you will get no logic. If you're using a buffer type port, that is really an output.

 

[win2010]

I`m searching for people who know about DVB-T2 because which is particular problem arias in design of Interleavers.....

 

[TrickyDicky]

I think you will struggle to find specialists. The problems you are describing appear to be coding errors.