problem getting signal to repeat

I'm using VHDL to generate a control signal and it's only doing one cycle. Does anyone know how to get the signal to repeat form more than one period?

if its a behavioral model then use some counter kind of thing to generate it..

It is behavioral and I have a counter but I must be missing something. Here is part of the code.
ENTITY control IS
PORT (clk : IN std_logic;
out1, out2, out3 : OUT std_logic);
END control;
ARCHITECTURE behavior OF control IS
--Calculated times for first phase pulses
CONSTANT TIMEA1:INTEGER:=698;
CONSTANT TIMEA2:INTEGER:=813;
CONSTANT TIMEA3:INTEGER:=1081;
CONSTANT TIMEA4:INTEGER:=11419;
CONSTANT TIMEA5:INTEGER:=11688;
CONSTANT TIMEA6:INTEGER:=11802;

BEGIN
PROCESS(clk)
VARIABLE counter:INTEGER:=0;
BEGIN
IF clk'event AND clk='1' THEN
IF counter<TIMEA1 THEN out1<='1';
ELSIF (counter>=TIMEA1 AND counter<TIMEA2) THEN out1<='0';
ELSIF (counter>=TIMEA2 AND counter<TIMEA3) THEN out1<='1';
ELSIF (counter>=TIMEA3 AND counter<TIMEA4) THEN out1<='0';
ELSIF (counter>=TIMEA4 AND counter<TIMEA5) THEN out1<='1';
ELSIF (counter>=TIMEA5 AND counter<TIMEA6) THEN out1<='0';
ELSIF (counter>=TIMEA6) THEN out1<='1';
END IF;
counter:=counter+1;
END IF;
END PROCESS;
END behavior;

you can pass through a flop and exor the flop o/p with flop i/p.