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Problem: Generate pads with ASIC DESIGN KIT (ADK)

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jpmdantas

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asic design kit

Hi,

I'm an engineering student working with analog ic layout. The deadline for our project is in 1 week. We already make the entire layout and post-layout simulation. However we get a problem when trying to put the padframe. the pad generator seems to be limited to 40 pins. The foundry request a minimum 5 mm2 chip. so, we need to improve this generated pad. Does anyone have an idea? Is this normal, or i did something wrong? How to make the pad generator create more than 40 pins?

We are using mentor tools - the ASIC Design Kit (ADK) v3.1


Best Regards,

and Hope you can help me.
 

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